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december 1994 order number: 290479-004 82434LX/82434nx pci, cache and memory controller (pcmc) y supports the pentium tm processor at icomp tm index 510 t 60 mhz and icomp index 567 t 66 mhz y supports the pentium processor at icomp index 735 t 90 mhz, icomp index 815 t 100 mhz, and icomp index 610 t 75 mhz y supports pipelined addressing capability of the pentium processor y the 82430nx drives 3.3v signal levels on the cpu and cache interfaces y high performance cpu/pci/memory interfaces via posted write and read prefetch buffers y fully synchronous pci interface with full bus master capability y supports the pentium processor internal cache in either write-through or write-back mode y programmable attribute map of dos and bios regions for system flexibility y integrated low skew clock driver for distributing host clock y integrated second level cache controller e integrated cache tag ram e write-through and write-back cache modes for the 82434LX e write-back for the 82434nx e 82434nx supports low-power cache standby e direct mapped organization e supports standard and burst srams e 256-kbyte and 512-kbyte sizes e cache hit cycle of 3-1-1-1 on reads and writes using burst srams e cache hit cycle of 3-2-2-2 on reads and 4-2-2-2 on writes using standard srams y integrated dram controller e supports 2 mbytes to 192 mbytes of cacheable main memory for the 82434LX e supports 2 mbytes to 512 mbytes of cacheable main memory for the 82434nx e supports dram access times of 70 ns and 60 ns e cpu writes posted to dram 4-1-1-1 e refresh cycles decoupled from isa refresh to reduce the dram access latency e six ras y lines (82434LX) e eight ras y lines (82434nx) e refresh by ras y -only, or cas- before-ras y , in single or burst of four y host/pci bridge e translates cpu cycles into pci bus cycles e translates back-to-back sequential cpu memory writes into pci burst cycles e burst mode writes to pci in zero pci wait-states (i.e. data transfer every cycle) e full concurrency between cpu-to- main memory and pci-to-pci transactions e full concurrency between cpu-to- second level cache and pci-to-main memory transactions e same cache and memory system logic design for isa and eisa systems e cache snoop filter ensures data consistency for pci-to-main memory transactions y 208-pin qfp package * other brands and names are the property of their respective owners.
82434LX/82434nx this document describes both the 82434LX and 82434nx. unshaded areas describe the 82434LX. shaded areas, like this one, describe 82434nx operations that differ from the 82434LX. the 82434LX/82434nx pci, cache, memory controllers (pcmc) integrate the cache and main memory dram control functions and provide bus control for transfers between the cpu, cache, main memory, and the pci local bus. the cache controller supports write-back (or write-through for 82434LX) cache policy and cache sizes of 256-kbytes and 512-kbytes. the cache memory can be implemented with either standard or burst srams. the pcmc cache controller integrates a high-performance tag ram to reduce system cost. 2
82434LX/82434nx 290479 1 note: ras [ 7:6 ] y and ma11 are only on the 82434nx. ccs [ 1:0 ] functionality is only on the 82434nx. simplified block diagram of the pcmc 3
82434LX/82434nx pci, cache and memory controller (pcmc) contents page 1.0 architectural overview 10 1.1 system overview 10 1.1.1 bus hierarchyeconcurrent operations 10 1.1.2 bus bridges 13 1.2 pcmc overview 13 1.2.1 cache operations 14 1.2.1.1 cache consistency 15 1.2.2 address/data paths 15 1.2.2.1 read/write buffers 15 1.2.3 host/pci bridge operations 15 1.2.4 dram memory operations 16 1.2.5 3.3v signals 16 2.0 signal descriptions 16 2.1 host interface 17 2.2 dram interface 22 2.3 cache interface 23 2.4 pci interface 24 2.5 lbx interface 28 2.6 reset and clock 28 3.0 register description 30 3.1 i/o mapped registers 31 3.1.1 confaddeconfiguration address register 31 3.1.2 cseeconfiguration space enable register 32 3.1.3 trceturbo-reset control register 33 3.1.4 forweforward register 34 3.1.5 pmcepci mechanism control register 34 3.1.6 confdataeconfiguration data register 34 3.2 pci configuration space mapped registers 35 3.2.1 configuration space access mechanism 36 3.2.1.1 access mechanism y 1: 36 3.2.1.2 access mechanism y 2 37 3.2.2 videvendor identification register 40 3.2.3 didedevice identification register 40 4
contents page 3.2.4 pcicmdepci command register 41 3.2.5 pcistsepci status register 42 3.2.6 riderevision identification register 43 3.2.7 rlpieregister-level programming interface register 43 3.2.8 subcesub-class code register 43 3.2.9 basecebase class code register 44 3.2.10 mltemaster latency timer register 44 3.2.11 bistebist register 44 3.2.12 hcsehost cpu selection register 45 3.2.13 dfcedeturbo frequency control register 46 3.2.14 sccesecondary cache control register 46 3.2.15 hbcehost read/write buffer control 48 3.2.16 pbcepci read/write buffer control register 49 3.2.17 dramcedram control register 50 3.2.18 dramtedram timing register 51 3.2.19 pameprogrammable attribute map registers (pam [ 6:0 ] ) 51 3.2.20 drbedram row boundary registers 54 3.2.20.1 82434LX description 54 3.2.20.2 82434nx description 56 3.2.21 drbeedram row boundary extension register 58 3.2.22 errcmdeerror command register 58 3.2.23 errstseerror status register 60 3.2.24 smrsesmram space register 61 3.2.25 msgememory space gap register 61 3.2.26 fbreframe buffer range register 62 4.0 pcmc address map 64 4.1 cpu memory address map 64 4.2 system management ramesmram 64 4.3 pc compatibility range 65 4.4 i/o address map 66 5
contents page 5.0 second level cache interface 67 5.1 82434LX cache 67 5.1.1 clock latencies (82434LX) 75 5.1.2 standard sram cache cycles (82434LX) 76 5.1.2.1 burst read (82434LX) 76 5.1.2.2 burst write (82434LX) 78 5.1.2.3 cache line fill (82434LX) 80 5.1.3 burst sram cache cycles (82434LX) 84 5.1.3.1 burst read (82434LX) 84 5.1.3.2 burst write (82434LX) 86 5.1.3.3 cache line fill (82434LX) 88 5.1.4 snoop cycles 90 5.1.5 flush, flush acknowledge and write-back special cycles 98 5.2 82434nx cache 98 5.2.1 cycle latency summary (82434nx) 102 5.2.2 standard sram cache cycles (82434nx) 103 5.2.3 second level cache standby 103 5.2.4 snoop cycles 103 5.2.5 flush, flush acknowledge, and write-back special cycles 103 6.0 dram interface 104 6.1 82434LX dram interface 104 6.1.1 dram configurations 105 6.1.2 dram address translation 105 6.1.3 cycle timing summary 108 6.1.4 cpu to dram bus cycles 108 6.1.4.1 read page hit 108 6.1.4.2 read page miss 110 6.1.4.3 read row miss 111 6.1.4.4 write page hit 112 6.1.4.5 write page miss 113 6.1.4.6 write row miss 114 6.1.4.7 read cycle, 0-active ras y mode 115 6.1.4.8 write cycle, 0-active ras y mode 116 6
contents page 6.1.5 refresh 117 6.1.5.1 ras y -only refresh-single 117 6.1.5.2 cas y -before-ras y refresh-single 119 6.1.5.3 hidden refresh-single 120 6.2 82434nx dram interface 121 6.2.1 dram address translation 121 6.2.2 cycle timing summary 122 6.2.3 cpu to dram bus cycles 122 6.2.3.1 burst dram read page hit 123 6.2.3.2 burst dram read page miss 124 6.2.3.3 burst dram read row miss 125 6.2.3.4 burst dram write page hit 126 6.2.3.5 burst dram write page miss 127 6.2.3.6 burst dram write row miss 128 6.2.4 refresh 129 6.2.4.1 ras y -only refreshesingle 129 6.2.4.2 cas y -before-ras y refreshesingle 130 6.2.4.3 hidden refresh-single 131 7.0 pci interface 132 7.1 pci interface overview 132 7.2 cpu-to-pci cycles 132 7.2.1 cpu write to pci 132 7.3 register access cycles 133 7.3.1 cpu write cycle to pcmc internal register 134 7.3.2 cpu read from pcmc internal register 135 7.3.3 cpu write to pci device configuration register 136 7.3.4 cpu read from pci device configuration register 138 7.4 pci-to-main memory cycles 141 7.4.1 pci master write to main memory 141 7.4.2 pci master read from main memory 143 7
contents page 8.0 system clocking and reset 144 8.1 clock domains 144 8.2 clock generation and distribution 144 8.3 phase locked loop circuitry 145 8.4 system reset 147 8.5 82434nx reset sequencing 149 9.0 electrical characteristics 150 9.1 absolute maximum ratings 150 9.2 thermal characteristics 150 9.3 82434LX dc characteristics 150 9.4 82434nx dc characteristics 152 9.5 82434LX ac characteristics 154 9.5.1 host clock timing, 66 mhz (82434LX) 154 9.5.2 cpu interface timing, 66 mhz (82434LX) 155 9.5.3 second level cache standard sram timing, 66 mhz (82434LX) 157 9.5.4 second level cache burst sram timing, 66 mhz (82434LX) 158 9.5.5 dram interface timing, 66 mhz (82434LX) 158 9.5.6 pci clock timing, 66 mhz (82434LX) 158 9.5.7 pci interface timing, 66 mhz (82434LX) 159 9.5.8 lbx interface timing, 66 mhz (82434LX) 160 9.5.9 host clock timing, 60 mhz (82434LX) 160 9.5.10 cpu interface timing, 60 mhz (82434LX) 161 9.5.11 second level cache standard sram timing, 60 mhz (82434LX) 163 9.5.12 second level cache burst sram timing, 60 mhz (82434LX) 164 9.5.13 dram interface timing, 60 mhz (82434LX) 164 9.5.14 pci clock timing, 60 mhz (82434LX) 165 9.5.15 pci interface timing, 60 mhz (82434LX) 165 9.5.16 lbx interface timing, 60 mhz (82434LX) 166 8
contents page 9.6 82434nx ac characteristics 167 9.6.1 host clock timing, 66 mhz (82434nx), preliminary 167 9.6.2 cpu interface timing, 66 mhz (82434nx), preliminary 168 9.6.3 second level cache standard sram timing, 66 mhz (82434nx), preliminary 170 9.6.4 second level cache burst sram timing, 66 mhz (82434nx), preliminary 171 9.6.5 dram interface timing, 66 mhz (82434nx), preliminary 171 9.6.6 pci clock timing, 66 mhz (82434nx), preliminary 172 9.6.7 pci interface timing, 66 mhz (82434nx), preliminary 172 9.6.8 lbx interface timing, 66 mhz (82434nx), preliminary 173 9.6.9 host clock timing, 50 and 60 mhz (82434nx) 173 9.6.10 cpu interface timing, 50 and 60 mhz (82434nx) 174 9.6.11 second level cache standard sram timing, 50 and 60 mhz (82434nx) 176 9.6.12 second level cache burst sram timing, 50 and 60 mhz (82434nx) 177 9.6.13 dram interface timing, 50 and 60 mhz (82434nx) 177 9.6.14 pci clock timing, 50 and 60 mhz (82434nx) 178 9.6.15 pci interface timing, 50 and 60 mhz (82434nx) 178 9.6.16 lbx interface timing, 50 and 60 mhz (82434nx) 179 9.6.17 timing diagrams 179 10.0 pinout and package information 182 10.1 pin assignment 182 10.2 package characteristics 189 11.0 testability 190 9
82434LX/82434nx 1.0 architectural overview this section provides an 82430lx/82430nx pciset system overview that includes a description of the bus hierarchy and bridges between the buses. the 82430lx pciset consists of the 82434LX pcmc and 82433lx lbx components plus either a pci/isa bridge or a pci/eisa bridge. the 82430nx pciset consists of the 82434nx pcmc and 82433nx lbx components plus either a pci/isa bridge or a pci/ eisa bridge. the pcmc and lbx provide the core cache and main memory architecture and serve as the host/pci bridge. an overview of the pcmc fol- lows the system overview section. 1.1 system overview the 82430lx/82430nx pciset provides the host/ pci bridge, cache and main memory controller, and an i/o subsystem core (either pci/eisa or pci/isa bridge) for the next generation of high-performance personal computers based on the pentium proces- sor. system designers can take advantage of the power of the pci (peripheral component intercon- nect) local bus while maintaining access to the large base of eisa and isa expansion cards. extensive buffering and buffer management within the bridges ensures maximum efficiency in all three buses (host cpu, pci, and eisa/isa buses). for an isa-based system, the pciset includes the system i/o (82378ib sio) component (figure 1) as the pci/isa bridge. for an eisa-based system (fig- ure 2), the pciset includes the pci-eisa bridge (82375eb pceb) and the eisa system component (82374eb esc). the pceb and esc work in tan- dem to form the complete pci/eisa bridge. 1.1.1. bus hierarchyeconcurrent operations systems based on the 82430lx/82430nx pciset contain three levels of buses structured in the fol- lowing hierarchy: # host bus as the execution bus # pci bus as a primary i/o bus # isa or eisa bus as a secondary i/o bus. this bus hierarchy allows concurrency for simulta- neous operations on all three buses. data buffering permits concurrency for operations that crossover into another bus. for example, the pentium proces- sor could post data destined to the pci in the lbx. this permits the host transaction to complete in minimum time, freeing up the host bus for further transactions. the pentium processor does not have to wait for the transfer to complete to its final desti- nation. meanwhile, any ongoing pci bus transac- tions are permitted to complete. the posted data is then transferred to the pci bus when the pci bus is available. the lbx implements extensive buffering for host-to-pci, host-to-main memory, and pci-to- main memory transactions. in addition, the pceb/ esc chip set and the sio implement extensive buff- ering for transfers between the pci bus and the eisa and isa buses, respectively. host bus designed to meet the needs of high-performance computing, the host bus features: # 64-bit data path # 32-bit address bus with address pipelining # synchronous frequencies of 60 mhz and 66 mhz # synchronous frequency of 50 mhz (82430nx) # burst read and write transfers # support for first level and second level caches # capable of full concurrency with the pci and memory subsystems # byte data parity # full support for pentium processor machine check and dos compatible parity reporting # support for pentium processor system manage- ment mode (smm). 10
82434LX/82434nx 290479 2 figure 1. block diagram of a 82430lx/82430nx pciset isa system pci bus the pci bus is designed to address the growing in- dustry needs for a standardized local bus that is not directly dependent on the speed and the size of the processor bus. new generations of personal com- puter system software such as windows tm and win-nt tm with sophisticated graphical interfaces, multi-tasking, and multi-threading bring new require- ments that traditional pc i/o architectures cannot satisfy. in addition to the higher bandwidth, reliability and robustness of the i/o subsystem are becoming increasingly important. pci addresses these needs and provides a future upgrade path. pci features in- clude: # processor independent # multiplexed, burst mode operation # synchronous at frequencies up to 33 mhz # 120 mbyte/sec usable throughput (132 mbyte/sec peak) for a 32-bit data path 11
82434LX/82434nx # low latency random access (60 ns write access latency to slave registers from a master parked on the bus) # capable of full concurrency with the processor/ memory subsystem # full multi-master capability allowing any pci mas- ter peer-to-peer access to any pci slave # hidden (overlapped) central arbitration # low pin count for cost effective component pack- aging (multiplexed address/data) # address and data parity # three physical address spaces: memory, i/o, and configuration # comprehensive support for autoconfiguration through a defined set of standard configuration functions. 290479 3 figure 2. block diagram of the 82430lx/82430nx pciset eisa system 12
82434LX/82434nx isa bus figure 1 represents a system using the isa bus as the second level i/o bus. it allows personal comput- er platforms built around the pci as a primary i/o bus to leverage the large isa product base. the isa bus has 24-bit addressing and a 16-bit data path. eisa bus figure 2 represents a system using the eisa bus as the second level i/o bus. it allows personal comput- er platforms built around the pci as a primary i/o bus to leverage the large eisa/isa product base. combinations of pci and eisa buses, both of which can be used to provide expansion functions, will sat- isfy even the most demanding applications. along with compatibility for 16-bit and 8-bit isa hard- ware and software, the eisa bus provides the fol- lowing key features: # 32-bit addressing and 32-bit data path # 33 mbyte/sec bus bandwidth # multiple bus master support through efficient arbi- tration # support for autoconfiguration. 1.1.2 bus bridges host/pci bridge chip set (pcmc and lbx) the pcmc and lbx enhance the system perform- ance by allowing for concurrency between the host cpu bus and pci bus, giving each greater bus throughput and decreased bus latency. the lbx contains posted write buffers for host-to-pci, host- to-main memory, and pci-to-main memory transfers. the lbx also contains read prefetch buffers for host reads of pci, and pci reads of main memory. there are two lbxs per system. the lbxs are con- trolled by commands from the pcmc. the pcmc/ lbx host/pci bridge chip set is covered in more detail in section 1.2, pcmc overview. pci-eisa bridge chip set (pceb and esc) the pceb provides the master/slave functions on both the pci bus and the eisa bus. functioning as a bridge between the pci and eisa buses, the pceb provides the address and data paths, bus controls, and bus protocol translation for pci-to- eisa and eisa-to-pci transfers. extensive data buff- ering in both directions increase system perform- ance by maximizing pci and eisa bus efficiency and allowing concurrency on the two buses. the pceb's buffer management mechanism ensures data coher- ency. the pceb integrates central bus control func- tions including a programmable bus arbiter for the pci bus and eisa data swap buffers for the eisa bus. integrated system functions include pci parity generation, system error reporting, and programma- ble pci and eisa memory and i/o address space mapping and decoding. the pceb also contains a bios timer that can be used to implement timing loops. the pceb is intended to be used with the esc to provide an eisa i/o subsystem interface. the esc integrates the common i/o functions found in today's eisa-based pcs. the esc incorpo- rates the logic for eisa bus controller, enhanced seven channel dma controller with scatter-gather support, eisa arbitration, 14 level interrupt control- ler, advanced programmable interrupt controller (apic), five programmable timer/counters, non- maskable-interrupt (nmi) control, and power man- agement. the esc also integrates support logic to decode peripheral devices (e.g., the flash bios, real time clock, keyboard/mouse controller, floppy con- troller, two serial ports, one parallel port, and ide hard disk drive). pci/isa bridge (sio): the sio component provides the bridge between the pci bus and the isa bus. the sio also inte- grates many of the common i/o functions found in today's isa-based pcs. the sio incorporates the logic for a pci interface (master and slave), isa in- terface (master and slave), enhanced seven channel dma controller that supports fast dma transfers and scatter-gather, data buffers to isolate the pci bus from the isa bus and to enhance performance, pci and isa arbitration, 14 level interrupt controller, a 16-bit bios timer, three programmable timer/coun- ters, and non-maskable-interrupt (nmi) control logic. the sio also provides decode for peripheral devices (e.g., the flash bios, real time clock, keyboard/ mouse controller, floppy controller, two serial ports, one parallel port, and ide hard disk drive). 1.2 pcmc overview the pcmc (along with the lbx) provides three basic functions: a cache controller, a main memory dram controller, and a host/pci bridge. this section pro- vides an overview of these functions. note that, in this document, operational descriptions assume that the pcmc and lbx components are used together. 13
82434LX/82434nx 1.2.1 cache operations the pcmc provides the control for a second level cache memory array implemented with either stan- dard asynchronous srams or synchronous burst srams. the data memory array is external to the pcmc and located on the host address/data bus. since the pentium processor contains an internal cache, there can be two separate caches in a host subsystem. the cache inside the pentium processor is referred to as the first level cache (also called primary cache). a detailed description of the first lev- el cache is beyond the scope of this document. the pcmc cache control circuitry and associated exter- nal memory array is referred to as the second level cache (also called secondary cache). the second level cache is unified, meaning that both cpu data and instructions are stored in the cache. the 82434LX pcmc supports both write-through and write-back caching policies and the 82434nx sup- ports write-back. the optional second level cache memory array can be either 256-kbytes or 512-kbytes in size. the cache is direct-mapped and is organized as either 8k or 16k cache lines of 32 bytes per line. in addition to the cache data ram, the second level cache contains a 4k set of cache tags that are inter- nal to the pcmc. each tag contains an address that is associated with the corresponding data sector (2 lines for a 256 kbyte cache and 4 lines for a 512 kbyte cache) and two status bits for each line in the sector. during a main memory read or write operation, the pcmc first searches the cache. if the addressed code or data is in the cache, the cycle is serviced by the cache. if the addressed code or data is not in the cache, the cycle is forwarded to main memory. for the write-through (82434LX only) and write-back (both 82434LX and 82434nx) policies, the cache operation is determined by the cpu read or write cycle as follows: write cycle if the caching policy is write-through and the write cycle hits in the cache, both the cache and main memory are updated. upon a cache miss, only main memory is updated. the cache is not updat- ed (no write-allocate). if the caching policy is write-back and the write cycle hits in the cache, only the cache is updated; main memory is not affected. upon a cache miss, only main memory is updated. the cache is not updated (no write-allocate). read cycle upon a cache hit, the cache operation is the same for both write-through and write-back. in this case, data is transferred from the cache to the cpu. main memory is not accessed. 290479 4 figure 3. second level cache organization 14
82434LX/82434nx if the read cycle causes a cache miss, the line containing the requested data is transferred from main memory to the cache and to the cpu. in the case of a write-back cache, if the cache line fill is to a sector containing one or more modified lines, the modified lines are written back to main memory and the new line is brought into the cache. for a modified line write-back operation, the pcmc transfers the modified cache lines to main memory via a write buffer in the lbx. before writing the last modified line from the write buffer to main memory, the pcmc updates the first and second level caches with the new line, allowing the cpu access to the requested data with minimum latency. 1.2.1.1 cache consistency the snoop mechanism in the pcmc ensures data consistency between cache (both first level and sec- ond level) and main memory. the pcmc monitors pci master accesses to main memory and when needed, initiates an inquire (snoop) cycle to the first and second level caches. the snoop mechanism guarantees that consistent data is always delivered to both the host cpu and pci masters. 1.2.2 address/data paths address paths between the cpu/cache and pci and data paths between the cpu/cache, pci, and main memory are supplied by two lbx components. the lbx is a companion component to the pcmc. together, they form a host/pci bridge. the pcmc (via the pcmc/lbx interface signals), controls the address and data flow through the lbxs. refer to the lbx data sheet for more details on the address and data paths. data is transferred to and from the pcmc internal registers via the pcmc address lines. when the host cpu performs a write operation, the data is sent to the lbxs. when the pcmc decodes the cy- cle as an access to one of its internal registers, it asserts ahold to the cpu and instructs the lbxs to copy the data onto the host address lines. when the pcmc decodes a host read as an access to a pcmc internal register, it asserts ahold to the cpu. the pcmc then places the register data on its address lines and instructs the lbx to copy the data on the host address bus to the host data bus. when the register data is on the host data bus, the pcmc negates ahold and completes the cycle. 1.2.2.1 read/write buffers the lbx provides an interface for the cpu address and data buses, pci address/data bus, and the main memory dram data bus. there are three post- ed write buffers and one read-prefetch buffers imple- mented in the lbxs to increase performance and to maximize concurrency. the buffers are: # cpu-to-main memory posted write buffer (4 qwords) # cpu-to-pci posted write buffer (4 dwords) # pci-to-main memory posted write buffer (2 x 4 dwords) # pci-to-main memory read prefetch buffer (line buffer, 4 qwords). refer to the lbx data sheet for details on the opera- tion of these buffers. 1.2.3 host/pci bridge operations the pcmc permits the host cpu to access devices on the pci bus. these accesses can be to pci i/o space, pci memory space, or pci configuration space. as a pci device, the pcmc can be either a master initiating a pci bus operation or a target responding to a pci bus operation. the pcmc is a pci bus master for host-to-pci cycles and a target for pci- to-main memory transfers. note that the pcmc does not permit peripherals to be located on the host bus. cpu i/o cycles, other than to pcmc internal registers, are forwarded to the pci bus and pci bus accesses to the host bus are not supported. when the cpu initiates a bus cycle to a pci device, the pcmc becomes a pci bus master and trans- lates the cpu cycle into the appropriate pci bus cycle. the host/pci posted write buffer in the lbxs permits the cpu to complete cpu-to-pci dword memory writes in three cpu clocks (1 wait-state), even if the pci bus is currently busy. the posted data is written to the pci device when the pci bus is available. when a pci bus master initiates a main memory ac- cess, the pcmc (and lbxs) become the target of the pci bus cycle and responds to the read/write access. during pci-to-main memory accesses, the pcmc automatically performs cache snoop opera- tions on the host bus, when needed, to maintain data consistency. 15
82434LX/82434nx as a pci device, the pcmc contains all of the re- quired pci configuration registers. the host cpu reads and writes these registers as described in section 3.0, register description. 1.2.4 dram memory operations the pcmc contains a dram controller that sup- ports cpu and pci master accesses to main memo- ry. the pcmc dram interface supplies the control signals and address lines and the lbxs supply the data path. dram parity is generated for main mem- ory writes and checked for memory reads. for the 82434LX, the memory array is 64-bits wide and ranges in size from 2 mbytes 192 mbytes. the array can be implemented with either single-sided or double-sided simms. dram simm sizes of 256k x 36, 1m x 36, and 4m x 36 are supported. for the 82434nx, the memory array is 64-bits wide and ranges in size from 2 mbytes 512 mbytes. the array can be implemented with either single-sided or double-sided simms. dram simm sizes of 256k x 36, 1m x 36, 4m x 36, and 16m x 36 are supported. to provide optimum support for the various cache configurations, and the resultant mix of bus cycles, the system designer can select between 0-active ras y and 1-active ras y modes. these modes af- fect the behavior of the ras y signal following either cpu-to-main memory cycles or pci-to-main memory cycles. the pcmc also provides programmable memory and cacheability attributes on 14 memory segments of various sizes in the isa compatibility range (512 kbyte 1 mbyte address range). access rights to these memory segments from the pci bus are controlled by the expansion bus bridge. the pcmc permits a gap to be created in main memory within the 1 mbyte 16 mbytes address range, accommodating isa devices which are mapped into this range (e.g., isa lan card or an isa frame buffer). 1.2.5 3.3v signals the 82434nx pcmc drives 3.3v signal levels on the cpu and second level cache interfaces. thus, no extra logic (i.e. 5v/3.3v translation) is required when interfacing to 3.3v processors and srams. six of the power pins on the 82434nx are vdd3 pins. these pins are connected to a 3.3v power supply. the vdd3 pins power the output buffers on the cpu and second level cache interfaces. the vdd3 pins also power the output buffers for the hclk [ a-f ] outputs. 2.0 signal descriptions this section provides a detailed description of each signal. the signals are arranged in functional groups according to their associated interface. the states of all of the signals during hard reset are provided in section 8.0, system clocking and reset. the `` y '' symbol at the end of a signal name indi- cates that the active, or asserted state occurs when the signal is at a low voltage level. when `` y '' is not present after the signal name, the signal is asserted when at the high voltage level. the terms assertion and negation are used exten- sively. this is done to avoid confusion when working with a mixture of ``active-low'' and ``active-high'' sig- nals. the term assert ,or assertion indicates that a signal is active, independent of whether that level is represented by a high or low voltage. the term ne- gate ,or negation indicates that a signal is inactive. the following notations are used to describe the sig- nal type. in input is a standard input-only signal out totem pole output is a standard active driver o/d open drain t/s tri-state is a bi-directional, tri-state input/out- put pin s/t/s sustained tri-state is an active low tri-state sig- nal owned and driven by one and only one agent at a time. the agent that drives a s/t/s pin low must drive it high for at least one clock before letting it float. a new agent can not start driving a s/t/s signal any sooner than one clock after the previous owner tri-states it. an external pull-up is required to sustain the inactive state until another agent drives it and must be provided by the central resource. 16
82434LX/82434nx 2.1 host interface signal type description a [ 31:0 ] t/s address bus: a [ 31:0 ] are the address lines of the host bus. a [ 31:3 ] are connected to the cpu a [ 31:3 ] lines and to the lbxs. a [ 2:0 ] are only connected to the lbxs. along with the byte enable signals, the a [ 31:3 ] lines define the physical area of memory or i/o being accessed. during cpu cycles, the a [ 31:3 ] lines are inputs to the pcmc. they are used for address decoding and second level cache tag lookup sequences. also during cpu cycles, a [ 2:0 ] are outputs and are generated from be [ 7:0 ] y .a [ 27:24 ] provide hardware strapping options for test features. for more details on theses options, refer to section 11.0 testability. during inquire cycles, a [ 31:5 ] are inputs from the lbxs to the cpu and the pcmc to snoop the first and the second level cache tags, respectively. in response to a flush or flush acknowledge special cycle, the pcmc asserts ahold and drives the addresses of the second level cache lines to be written back to main memory on a [ 18:7 ] . during cpu to pci configuration cycles, the pcmc drives a [ 31:0 ] with the pci configuration space address that is internally derived from the cpu physical i/o address. all pcmc internal configuration registers are accessed via a [ 31:0 ] . during cpu reads from pcmc internal configuration registers, the pcmc asserts ahold and drives the contents of the addressed register on a [ 31:0 ] . the pcmc then signals the lbxs to copy this value from the address lines onto the host data lines. during writes to pcmc internal configuration registers, the pcmc asserts ahold and signals the lbxs to copy the write data onto the a [ 31:0 ] lines. finally, when in deturbo mode, the pcmc periodically asserts ahold and then drives a [ 31:0 ] to valid logic levels to keep these lines from floating for an extended period of time. a [ 31:28 ] provide hardware strapping options at powerup. for more details on strapping options, refer to section 8.0, system clocking and reset. a [ 27:24 ] provide hardware strapping options for test features. for more details on these options, refer to section 11.0 testability. 17
82434LX/82434nx signal type description be [ 7:0 ] y in byte enables: the byte enables indicate which byte lanes on the cpu data bus carry valid data during the current bus cycle. in the case of cacheable reads, all 8 bytes of data are driven to the pentium processor, regardless of the state of the byte enables. the byte enable signals indicate the type of special cycle when m/io y e d/c y e 0 and w/r y e 1. during special cycles, only one byte enable is asserted by the cpu. the following table depicts the special cycle types and their byte enable encodings: special cycle type asserted byte enable shutdown be0 y flush be1 y halt/stop grant be2 y write back be3 y flush acknowledge be4 y branch trace message be5 y when the pcmc decodes a shutdown special cycle, it asserts ahold, drives 000...000 (the pci shutdown special cycle encoding) on the a [ 31:0 ] lines and signals the lbxs to latch the host address bus. the pcmc then drives a special cycle on pci, signaling the lbxs to drive the latched address (00...00) on the ad [ 31:0 ] lines during the data phase. the pcmc then asserts init for 16 hclks. in response to flush and flush acknowledge special cycles, the pcmc internally inspects the valid and modified bits for each of the second level cache sectors. if a line is both valid and modified, the pcmc drives the cache address of the line on the a [ 18:7 ] and caa/cab [ 6:3 ] lines and writes the line back to main memory. the valid and modified bits are both reset to 0. all valid and unmodified lines are simply marked invalid. in response to a write back special cycle, the pcmc simply returns brdy y to the cpu. the second level cache will be written back to main memory in response to the following flush special cycle. if be2 y is asserted during a special cycle, the 82434nx uses a4 to determine if the cycle is a halt or stop grant special cycle. if a4 e 0, the cycle is a halt special cycle and if a4 e 1, the cycle is a stop grant special cycle. in response to a halt special cycle, the pcmc asserts ahold, drives 000...001 (the pci halt special cycle encoding) on the a [ 31:0 ] lines, and signals the lbxs to latch the host address bus. the pcmc then drives a special cycle on pci, signaling the lbxs to drive the latched address (00...01) on the ad [ 31:0 ] lines during the data phase. when the 82434nx pcmc detects a cpu stop grant special cycle (m/io y e 0, d/c y e 0, w/r y e 1, a4 e 1, be [ 7:0 ] y e fbh), it generates a pci stop grant special cycle, with 0002h in the message field (ad [ 15:0 ] ) and 0012h in the message dependent data field (ad [ 31:16 ] ) during the first data phase (irdy y asserted). ads y in address strobe: the pentium processor asserts ads y to indicate that a new bus cycle is beginning. ads y is driven active in the same clock as the address, byte enable, and cycle definition signals. the pcmc ignores a floating low ads y that may occur when boff y is asserted as the cpu is asserting ads y . 18
82434LX/82434nx signal type description brdy y out burst ready: brdy y indicates that the system has responded in one of three ways: 1. valid data has been placed on the pentium processor data pins in response to a read, 2. cpu write data has been accepted by the system, or 3. the system has responded to a special cycle. na y out next address: the pcmc asserts na y for one clock when the memory system is ready to accept a new address from the cpu, even if all data transfers for the current cycle have not completed. the cpu may drive out a pending cycle two clocks after na y is asserted and has the ability to support up to two outstanding bus cycles. ahold out address hold: the pcmc asserts ahold to force the pentium processor to stop driving the address bus so that either the pcmc or lbxs can drive the bus. during pci master cycles, ahold is asserted to allow the lbxs to drive a snoop address onto the address bus. if the pci master locks main memory, ahold remains asserted until the pci master locked sequence is complete and the pci master negates plock y . ahold is asserted during all accesses to pcmc internal configuration registers to allow configuration register accesses to occur over the a [ 31:0 ] lines. when in deturbo mode, the pcmc periodically asserts ahold to prevent the processor from initiating bus cycles in order to emulate a slower system. the duration of ahold assertion in deturbo mode is controlled by the deturbo frequency control register (offset 51h). when pwrok is negated, the pcmc asserts ahold to allow the strapping options on a [ 31:28 ] to be read. for more details on strapping options, see the system clocking and reset section. eads y out external address strobe: the pcmc asserts eads y to indicate to the pentium processor that a valid snoop address has been driven onto the cpu address lines to perform an inquire cycle. during pci master cycles, the pcmc signals the lbxs to drive a snoop address onto the host address lines and then asserts eads y to cause the cpu to sample the snoop address. inv out invalidate: the inv signal specifies the final state (invalid or shared) that a first level cache line transitions to in the event of a cache line hit during a snoop cycle. when snooping the caches during a pci master write, the pcmc asserts inv with eads y . when inv is asserted with eads y , an inquire hit results in the line being invalidated. when snooping the caches during a pci master read, the pcmc does not assert inv with eads y . in this case, an inquire cycle hit results in a line transitioning to the shared state. boff y out backoff: the pcmc asserts boff y to force the pentium processor to abort all outstanding bus cycles that have not been completed and float its bus in the next clock. the pcmc uses this signal to force the cpu to re-order a write-back due to a snoop cycle around a currently outstanding bus cycle. the pcmc also asserts boff y to obtain the cpu data bus for write-back cycles from the secondary cache due to a snoop hit. the cpu remains in bus hold until boff y is negated. hitm y in hit modified: the pentium processor asserts hitm y to inform the pcmc that the current inquire cycle hit a modified line. hitm y is asserted by the pentium processor two clocks after the assertion of eads y if the inquire cycle hits a modified line in the primary cache. 19
82434LX/82434nx signal type description m/io y in bus cycle definition (memory/input-output, data/control, write/ read): m/io, d/c y and w/r y define host bus cycles as shown in the table below. d/c y w/r y m/io y d/c y w/r y bus cycle type low low low interrupt acknowledge low low high special cycle low high low i/o read low high high i/o write high low low code read high low high reserved high high low memory read high high high memory write interrupt acknowledge cycles are forwarded to the pci bus as pci interrupt acknowledge cycles (i.e. c/be [ 3:0 ] y e 0000 during the address phase). all i/o cycles and any memory cycles that are not directed to memory controlled by the pcmc dram controller are forwarded to pci. the pentium processor generates six different types of special cycles. the special cycle type is encoded on the be [ 7:0 ] y lines. hlock y in host bus lock: the pentium processor asserts hlock y to indicate the current bus cycle is locked. hlock y is asserted in the first clock of the first locked bus cycle and is negated after the brdy y is returned for the last locked bus cycle. the pentium processor guarantees hlock y to be negated for at least one clock between back-to- back locked operations. when a cpu locked cycle is directed to main memory, the pcmc guarantees that once the locked operation begins in main memory, the cpu has exclusive access to main memory (i.e., pci master accesses to main memory will not be initiated until the cpu locked operation completes). when a cpu locked cycle is directed to pci, the pcmc arbitrates for plock y (pci lock y ) before initiating the cycle on pci, except when the cycle is to the memory range defined by the frame buffer range register and the no lock requests bit in that register is set to 1. cache y in cacheability: the pentium processor asserts cache y to indicate the internal cacheability of a read cycle or that a write cycle is a burst write-back cycle. if the cpu drives cache y inactive during a read cycle, the returned data is not cached, regardless of the state of ken y . the cpu asserts cache y for cacheable data reads, cacheable code fetches, and cache line write-backs. cache y is driven along with the cycle definition pins. ken y out cache enable: the pcmc asserts ken y to indicate to the cpu that the current cycle is cacheable. ken y is asserted for all accesses to memory ranges 0 512-kbytes and 1024-kbytes to the top of main memory controlled by the pcmc when the primary cache enable bit is set to 1, except in the following case: ken y is not asserted for accesses to the top 64-kbyte of main memory controlled by the pcmc when the smram enable bit in the dram control register (offset 57h) is set to 1 and the area is not write protected. if the area is write protected and cacheable, ken y is asserted for code read cycles, but is not asserted during data read cycle. ken y is asserted for any cpu access within the range of 512-kbytes 1024-kbytes if the corresponding cache enable bit in the pam [ 6:0 ] registers (offsets 59h 5fh) is set to 1. when the pentium processor indicates that the current read cycle can be cached by asserting cache y and the pcmc responds with ken y , the cycle is converted into a burst cache line fill. the cpu samples ken y with the first of either brdy y or na y . 20
82434LX/82434nx signal type description smiact y in system management interrupt active: the pentium processor asserts smiact y to indicate that the processor is operating in system management mode (smm). when the smram enable bit in the dram control register (offset 57h) is set to 1, the pcmc allows cpu accesses smram as permitted by the smram space register at configuration space offset 72h. pen y out parity enable: the pen y signal, along with the mce bit in cr4 of the pentium processor, determines whether a machine check exception will be taken by the cpu as a result of a parity error on a read cycle. the pcmc asserts pen y during dram read cycles if the mchk on dram/l2 cache data parity error enable bit in the error command register (offset 70h) is set to 1. the pcmc asserts pen y during cpu second level cache read cycles if the mchk on dram/l2 cache data parity error enable and the l2 cache parity enable bits in the error command register (offset 70h) are both set to 1. pchk y in data parity check: pchk y is sampled by the pcmc to detect parity errors on cpu read cycles from main memory if the parity error mask enable bit in the dram control register (offset 57h) is reset to 0. pchk y is sampled by the pcmc to detect parity errors on cpu read cycles from the second level cache if the l2 cache parity enable bit in the error command register (offset 70h) is set to 1. if incorrect parity was detected on a data read, the pchk y signal is asserted by the pentium processor two clocks after brdy y is returned. pchk y is asserted for one clock for each clock in which a parity error was detected. 21
82434LX/82434nx 2.2 dram interface signal type description ras [ 5:0 ] y out row address strobes: the ras [ 5:0 ] y signals are used to latch the row address on the ma [ 10:0 ] lines into the drams. each ras [ 5:0 ] y signal corresponds to one dram row. the 82434LX pcmc supports up to 6 rows in the dram array. each row is eight bytes wide. these signals drive the ras y lines of the dram array directly, without external buffers. ras [ 7:6 ] y out row address strobes: the 82434nx supports up to eight rows of dram. ras [ 7:6 ] y are used with ras [ 5:0 ] to latch the row address on the ma [ 11:0 ] lines into the drams. each row is eight bytes wide. these signals drive the ras y lines of the dram array directly, without external buffers. cas [ 7:0 ] y out column address strobes: the cas [ 7:0 ] y signals are used to latch the column address on the ma [ 10:0 ] lines into the drams. each cas [ 7:0 ] y signal corresponds to one byte of the eight byte-wide array. these signals drive the cas y lines of the dram array directly, without external buffers. in a minimum configuration, each cas [ 7:0 ] y line only has one simm load, while the maximum configuration has 6 simm loads. we y out dram write enable: we y is asserted during both cpu and pci master writes to main memory. during burst writes to main memory, we y is asserted before the first assertion of cas [ 7:0 ] y and is negated with the last cas [ 7:0 ] y . the we y signal is externally buffered to drive the we y inputs on the drams. ma [ 10:0 ] out dram multiplexed address: ma [ 10:0 ] provide the row and column address to the dram array. the 82434LX uses ma [ 10:0 ] for the complete dram address bus. the ma [ 10:0 ] lines are externally buffered to drive the multiplexed address lines of the dram array. ma11 out dram multiplexed address: ma11 provides the extra addressability for the 16m x 36 simms that are supported by the 82434nx. ma [ 11:0 ] provide the row and column address to the dram array. like ma [ 10:0 ] , ma11 is externally buffered to drive the multiplexed address lines of the dram array. 22
82434LX/82434nx 2.3 cache interface signal type description cale out cache address latch enable: cale controls the external latch between the host address lines and the cache address lines. cale is asserted to open the external latch, allowing the host address lines to propagate to the cache address lines. cale is negated to latch the cache address lines. cads [ 1:0 ] y , out this signal pin has two functions, depending on the type of srams used for the second level cache. cr/w [ 1:0 ] y cache address strobe: cads [ 1:0 ] y are used with burst srams. when asserted, cads [ 1:0 ] y cause the burst srams to latch the cache address on the rising edge of hclk. cads [ 1:0 ] y are glitch-free synchronous signals. cads [ 1:0 ] y functionality is selected by the sram type bit in the secondary cache control register. two copies of this signal are provided for timing reasons only. cache read/write: cr/w y provide read/write control to the second level cache when using asynchronous dual-byte select srams. this functionality is selected by the sram type and cache byte control bits in the secondary cache control register. the two copies of this signal are always driven to the same logic level. cadv [ 1:0 ] y , out this signal pin has two functions. the cache chip select function is only enabled when the sram connectivity bit (bit 2) in the scc register is set to 1. ccs [ 1:0 ] y cache advance: cadv [ 1:0 ] y are used with burst srams to advance the internal two bit address counter inside the srams to the next address of the burst sequence. two copies of this signal are provided for timing reasons only. the two copies are always driven to the same logic level. cache chip select: ccs [ 1:0 ] y are used with asynchronous srams to de- select the srams, placing them in a low power standby mode. when the cpu runs a halt or stop grant special cycle, the 82434nx negates ccs [ 1:0 ] y , placing the second level cache in a power saving mode. the pcmc then asserts ccs [ 1:0 ] y (activating the srams) when the cpu asserts ads y . when using burst srams, only ccs1 y implements the ccs y function. cadv0 y retains the address advance function. ccs1 y serve two purposes with burst srams: 1) it is used (along with cads [ 1:0 ] y ) to place the srams in a low power standby mode. when the cpu runs a halt or stop grant special cycle, the 82434nx negates ccs1 y and asserts cads [ 1:0 ] y for one clock, placing the srams in a power saving mode. the pcmc then asserts ccs1 y so that the next ads y from the cpu places the srams in an active mode. 2) ccs1 y is used to block pipelined cycles from the srams when the srams are servicing a cycle. after na y is asserted, the pcmc negates ccs1 y preventing the srams from sampling a new address. ccs1 y is asserted again when the srams have completed the current cycle. caa [ 6:3 ] out cache address [ 6:3 ] : caa [ 6:3 ] and cab [ 6:3 ] are connected to address lines a [ 3:0 ] on the second level cache srams. caa [ 4:3 ] and cab [ 4:3 ] are used with cab [ 6:3 ] standard srams to advance through the burst sequence. caa [ 6:5 ] and cab [ 6:5 ] are used during second level cache write-back cycles to address the modified lines within the addressed sector. two copies of these signals are provided for timing reasons only. the two copies are always driven to the same logic level. 23
82434LX/82434nx signal type description coe [ 1:0 ] y out cache output enable: coe [ 1:0 ] y are asserted when data is to be read from the second level cache and are negated at all other times. two copies of this signal are provided for timing reasons only. the two copies are always driven to the same logic level. cwe [ 7:0 ] y , out this signal pin has two functions, depending on the type of srams used for the second level cache. cbs [ 7:0 ] y cache write enables: cwe [ 7:0 ] y are asserted to write data to the second level cache srams on a byte-by-byte basis. cwe7 y controls the most significant byte while cwe0 y controls the least significant byte. these signals are cache write enables when using burst srams (sram type bit in scc register is 1) or when using asynchronous srams (sram type bit in scc register is 0) and the cache byte control bit is 1. cache byte selects: the cbs [ 7:0 ] y lines provide byte control to the secondary cache when using dual-byte select asynchronous srams. these signals are cache byte select lines when the sram type and cache byte control bits in the scc register are both 0. 2.4 pci interface signal type description c/be [ 3:0 ] y t/s pci bus command and byte enables: c/be [ 3:0 ] y are driven by the current bus master during the address phase of a pci cycle to define the pci command, and during the data phase as the pci byte enables. the pci commands indicate the current cycle type, and the pci byte enables indicate which byte lanes carry meaningful data. c/be [ 3:0 ] y are outputs of the pcmc during cpu cycles that are directed to pci. c/be [ 3:0 ] y are inputs when the pcmc acts as a slave. the command encodings and types are listed below. c/be [ 3:0 ] y command 0000 interrupt acknowledge 0001 special cycle 0010 i/o read 0011 i/o write 0100 reserved 0101 reserved 0110 memory read 0111 memory write 1000 reserved 1001 reserved 1010 configuration read 1011 configuration write 1100 memory read multiple 1101 reserved 1110 memory read line 1111 memory write and invalidate 24
82434LX/82434nx signal type description frame y s/t/s cycle frame: frame y is driven by the current bus master to indicate the beginning and duration of an access. frame y is asserted to indicate that a bus transaction is beginning. while frame y is asserted, data transfers continue. when frame y is negated, the transaction is in the final data phase. frame y is an output of the pcmc during cpu cycles which are directed to pci. frame y is an input to the pcmc when the pcmc acts as a slave. irdy y s/t/s initiator ready: the assertion of irdy y indicates the current bus master's ability to complete the current data phase. irdy y works in conjunction with trdy y to indicate when data has been transferred. on pci, data is transferred on each clock that both irdy y and trdy y are asserted. during read cycles, irdy y is used to indicate that the master is prepared to accept data. during write cycles, irdy y is used to indicate that the master has driven valid data on the ad [ 31:0 ] lines. wait states are inserted until both irdy y and trdy y are asserted together. irdy y is an output of the pcmc when the pcmc is the pci master. irdy y is an input to the pcmc when the pcmc acts as a slave. trdy y s/t/s target ready: trdy y indicates the target device's ability to complete the current data phase of the transaction. it is used in conjunction with irdy y . a data phase is completed on each clock that trdy y and irdy y are both sampled asserted. during read cycles, trdy y indicates that valid data is present on ad [ 31:0 ] lines. during write cycles, trdy y indicates the target is prepared to accept data. wait states are inserted on the bus until both irdy y and trdy y are asserted together. trdy y is an output of the pcmc when the pcmc is the pci slave. trdy y is an input to the pcmc when the pcmc is a master. devsel y s/t/s device select: when asserted, devsel y indicates that the driving device has decoded its address as the target of the current access. devsel y is an output of the pcmc when pcmc is a pci slave and is derived from the memcs y input. memcs y is generated by the expansion bus bridge as a decode to the main memory address space. during cpu-to-pci cycles, devsel y is an input. it is used to determine if any device has responded to the current bus cycle, and to detect a target abort cycle. master-abort termination results if no subtractive decode agent exists in the system, and no one asserts devsel y within a programmed number of clocks. stop y s/t/s stop: stop y indicates that the current target is requesting the master to stop the current transaction. this signal is used in conjunction with devsel y to indicate disconnect, target-abort, and retry cycles. when pcmc is acting as a master on pci, if stop y is sampled active on a rising edge of pclkin, frame y is negated within a maximum of 3 clock cycles. stop y may be asserted by the pcmc in three cases. if a pci master attempts to access main memory when another pci master has locked main memory, the pcmc asserts stop y to signal retry. the pcmc detects this condition when sampling frame y and lock y both active during an address phase. when a pci master is reading from main memory, the pcmc asserts stop y when the burst cycle is about to cross a cache line boundary. when a pci master is writing to main memory, the pcmc asserts stop y upon filling either of the two pci-to-main memory posted write buffers. once asserted, stop y remains asserted until frame y is negated. 25
82434LX/82434nx signal type description plock y s/t/s pci lock: plock y is used to indicate an atomic operation that may require multiple transactions to complete. pci provides a mechanism referred to as ``resource lock'' in which only the target of the pci transaction is locked. the assertion of gnt y on pci does not guarantee control of the plock y signal. control of plock y is obtained under its own protocol. when the pcmc is the pci slave, plock y is sampled as an input on the rising edge of pclkin when frame y is sampled active. if plock y is sampled asserted, the pcmc enters into a locked state and remains in the locked state until plock y is sampled negated on a following rising edge of pclkin, when frame y is sampled asserted. req y out request: the pcmc asserts req y to indicate to the pci bus arbiter that the pcmc is requesting use of the pci bus in response to a cpu cycle directed to pci. gnt y in grant: when asserted, gnt y indicates that access to the pci bus has been granted to the pcmc by the pci bus arbiter. memcs y in main memory chip select: when asserted, memcs y indicates to the pcmc that a pci master cycle is targeting main memory. memcs y is generated by the expansion bus bridge. memcs y is sampled by the pcmc on the rising edge of pclkin on the first and second cycle after frame y has been asserted. flshreq y in flush request: when asserted, flshreq y instructs the pcmc to flush the cpu-to-pci posted write buffer in the lbxs and to disable further posting to this buffer as long as flshreq y remains active. the pcmc acknowledges completion of the cpu-to-pci write buffer flush operation by asserting memack y . memack y remains asserted until flshreq y is negated. flshreq y is driven by the expansion bus bridge and is used to avoid deadlock conditions on the pci bus. memreq y in memory request: when asserted, memreq y instructs the pcmc to flush the cpu-to-pci and cpu-to-main memory posted write buffers and to disable posting in these buffers as long as memreq y is active. the pcmc acknowledges completion of the flush operations by asserting memack y . memack y remains asserted until memreq y is negated. memreq y is driven by the expansion bus bridge. memack y out memory acknowledge: when asserted, memack y indicates the completion of the operations requested by an active flshreq y and/or memreq y . par t/s parity: par is an even parity bit across the ad [ 31:0 ] and c/be [ 3:0 ] y lines. parity is generated on all pci transactions. as a master, the pcmc generates even parity on cpu writes to pci, based on the ppout [ 1:0 ] inputs from the lbxs. during cpu read cycles from pci, the pcmc checks parity by checking the value sampled on the par input with the ppout [ 1:0 ] inputs from the lbxs. as a slave, the pcmc generates even parity on par, based on the ppout [ 1:0 ] inputs during pci master reads from main memory. during pci master writes to main memory, the pcmc checks parity by checking the value sampled on par with the ppout [ 1:0 ] inputs. 26
82434LX/82434nx signal type description perr y s/t/s parity error: perr y may be pulsed by any agent that detects a parity error during an address phase, or by the master or the selected target during any data phase in which the ad lines are inputs. the perr y signal is enabled when the perr y on receiving data parity error bit in the error command register (offset 70h) and the parity error enable bit in the pci command register (offset 04h) are both set to 1. when enabled, cpu-to-pci write data is checked for parity errors by sampling the perr y signal two pci clocks after data is driven. also, when enabled, perr y is asserted by the pcmc when it detects a data parity error on cpu read data from pci and pci master write data to main memory. perr y is neither sampled nor driven by the pcmc when either the perr y on receiving data parity error bit in the error command register or the parity error enable bit in the pci command register is reset to 0. serr y o/d system error: serr y may be pulsed by any agent for reporting errors other than parity. serr y is asserted by the pcmc whenever a serious system error (not necessarily a pci error) occurs. the intent is to have the pci central agent (for example, the expansion bus bridge) assert nmi to the processor. control over the serr y signal is provided via the error command register (offset 70h) when the parity error enable bit in the pci command register (offset 04h) is set to 1. when the serr y dram/l2 cache data parity error bit is set to 1, serr y is asserted upon detecting a parity error on cpu read cycles from dram. if the l2 cache parity bit is also set to 1, serr y will be asserted upon detecting a parity error on cpu read cycles from the second level cache. the pentium processor indicates these parity errors to the pcmc via the pchk y signal. when the serr y on pci address parity error bit is set to 1, the pcmc asserts serr y if a parity error is detected during the address phase of a pci master cycle. when the serr y on received pci data parity bit is set to 1, the pcmc asserts serr y if a parity error is detected on pci during a cpu read from pci. during cpu to pci write cycles, when the serr y on transmitted pci data parity error bit is set to 1, the pcmc asserts serr y in response to sampling perr y active. when the serr y on received target abort bit is set to 1, the pcmc asserts serr y when the pcmc receives a target abort on a pcmc initiated pci cycle. if the parity error enable bit in the pci command register is reset to 0, serr y is disabled and is never asserted by the pcmc. 27
82434LX/82434nx 2.5 lbx interface signal type description hig [ 4:0 ] out host interface group: hig [ 4:0 ] are outputs of the pcmc used to control the lbx ha (host address) and hd (host data) buses. commands driven on hig [ 4:0 ] cause the host data and/or address lines to be either driven or latched by the lbxs. see the 82433lx (lbx) local bus accelerator data sheet for a listing of the hig [ 4:0 ] commands. mig [ 2:0 ] out memory interface group: mig [ 2:0 ] are outputs of the pcmc and control the lbx md (memory data) bus. commands driven on the mig [ 2:0 ] lines cause the memory data lines to be either driven or latched by the lbxs. see the 82433lx (lbx) local bus accelerator data sheet for a listing of the mig [ 2:0 ] commands. mdle out memory data latch enable: during cpu reads from main memory, mdle is used to control the latching of memory read data on the cpu data bus. mdle is negated as cas [ 7:0 ] y are negated to close the latch between the memory data bus and the host data bus. during cpu reads from main memory, the pcmc closes the memory data to host data latch in the lbxs as brdy y is asserted and opens the latch after the cpu has sampled the data. pig [ 3:0 ] out pci interface group: pig [ 3:0 ] are outputs of the pcmc used to control the lbx ad (pci address/data) bus. commands driven on the pig [ 3:0 ] lines cause the ad lines to be either driven or latched. see the 82433lx (lbx) local bus accelerator data sheet for a listing of the pig [ 3:0 ] commands. drvpci out drive pci: drvpci acts as an output enable for the lbx ad lines. when sampled asserted, the lbxs begin driving the pci ad lines. when negated, the ad lines on the lbxs are tri-stated. the lbx ad lines are tri-stated asynchronously from the falling edge of drvpci. eol in end of line: eol is asserted by the low order lbx when a pci master read or write transaction is about to overrun a cache line boundary. eol has an internal pull- up resistor inside the pcmc. the low order lbx eol signal connects to this pcmc input. the high order lbx eol signal is connected to ground through an external pull-down resistor. ppout [ 1:0 ] in pci parity out: these signals reflect the parity of the 32 ad lines driven from or latched in the lbxs, depending on the command driven on pig [ 3:0 ] . the ppout0 pin has a weak internal pull-down resistor. the ppout1 pin has a weak internal pull- up resistor. 2.6 reset and clock signal type description hclkosc in host clock oscillator: the hclkosc input is driven externally by a crystal oscillator. the pcmc generates six copies of hclk from hclkosc (hclka hclkf). during power-up, hclkosc must stabilize for 1 ms before pwrok is asserted. if an external clock driver is used to clock the cpu, pcmc, lbxs and second level cache srams instead of the hclka hclkf outputs, hclkosc must be tied either high or low. hclka hclkf out host clock outputs: hclka hclkf are six low skew copies of the host clock. these outputs eliminate the need for an external low skew clock driver. 28
82434LX/82434nx signal type description hclkin in host clock input: all timing on the host, dram and second level cache interfaces is based on hclkin. if an external clock driver is used to clock the cpu, pcmc, lbxs and second level cache srams, the externally generated clock must be connected to hclkin. during power-up hclkin must stabilize for 1 ms before pwrok is asserted. cpurst out cpu hard reset: the cpurst pin is asserted in response to one of two conditions. powerup 82434LX: during powerup the 82434LX asserts cpurst when pwrok is negated. when pwrok is asserted, the 82434LX first ensures that it has been initialized before negating cpurst. 82434nx: during powerup, the 82434nx pcmc negates cpurst while pwrok is negated. when pwrok is asserted, the 82434nx asserts cpurst for 2 ms. software cpurst is also asserted when the system hard reset enable bit in the turbo-reset control register (i/o address 0cf9h) is set to 1 and the reset cpu bit toggles from 0 to 1 (82434LX and 82434nx). cpurst is driven synchronously to the rising edge of hclkin. init out initialization: init is asserted in response to any one of two conditions. when the system hard reset enable bit in the turbo-reset control register is reset to 0 and the reset cpu bit toggles from 0 to 1, the pcmc initiates a soft reset by asserting init. the pcmc also initiates a soft reset by asserting init in response to a shutdown special cycle. in both cases, init is asserted for a minimum of 2 host clocks. pwrok in power ok: when asserted, pwrok is an indication to the pcmc that power and hclkin have stabilized for at least 1 ms. pwrok can be driven asynchronously. 82434LX: when pwrok is negated, the 82434LX asserts both cpurst and pcirst y . when pwrok is driven high, the 82434LX ensures that it is initialized before negating cpurst and pcirst y . 82434nx: when pwrok is negated, the 82434nx negates cpurst and asserts pcirst y . when pwrok is asserted, the 82434nx asserts cpurst for 2 ms. pcirst y is negated 1 ms after pwrok is asserted. pclkout out pci clock output: pclkout is internally generated by a phase locked loop (pll) that divides the frequency of hclkin by 2. this output must be buffered externally to generate multiple copies of the pci clock. one of the copies must be connected to the pclkin pin. 29
82434LX/82434nx signal type description pclkin in pci clock input: an internal pll locks pclkin in phase with hclkin. all timing on the pcmc pci interface is referenced to the pclkin input. all output signals on the pci interface are driven from pclkin rising edges and all input signals on the pci interface are sampled on pclkin rising edges. pcirst y out pci reset: pcirst y is asserted to initiate hard reset on pci. pcirst y is asserted in response to one of two conditions. power-up during power-up the pcmc asserts pcirst y when pwrok is negated. 82434LX: when pwrok is asserted the pcmc will first ensure that it has been initialized before negating pcirst y . 82434nx: when pwrok is negated, the 82434nx asserts pcirst y . the 82434nx then negates pcirst y 1 ms after pwrok is asserted. software pcirst y is also asserted when the system hard reset enable bit in the turbo/reset control register is set to 1 and the reset cpu bit toggles from 0 to 1 (82434LX and 82434nx). pcirst y is driven asynchronously. testen in test enable: testen must be tied low for normal system operation. 3.0 register description the 82434LX/82434nx pcmc contains two sets of software accessible registers. these registers are ac- cessed via the host cpu i/o address space. the pcmc also contains a set of configuration registers that reside in pci configuration space and are used to specify pci configuration, dram configuration, cache configuration, operating parameters and optional system features (see section 3.2, pci configuration space mapped registers). the pcmc internal registers (both i/o mapped and configuration registers) are only accessible by the host cpu and cannot be accessed by pci masters. the registers can be accessed as byte, word (16-bit), or dword (32-bit) quantities. all multi-byte numeric fields use ``little-endian'' ordering (i.e., lower addresses contain the least significant parts of the field). some of the pcmc registers described in this section contain reserved bits. these bits are labeled ``r''. software must deal correctly with fields that are reserved. on reads, software must use appropriate masks to extract the defined bits and not rely on reserved bits being any particular value. on writes, software must ensure that the values of reserved bit positions are preserved. that is, the values of reserved bit positions must first be read, merged with the new values for other bit positions and then written back. in addition to reserved bits within a register, the pcmc contains address locations in the pci configuration space that are marked ``reserved'' (table 1). the pcmc responds to accesses to these address locations by completing the host cycle. when a reserved register location is read, 0000h is returned. writes to reserved registers have no affect on the pcmc. upon receiving a hard reset via the pwrok signal, the pcmc sets its internal configuration registers to predetermined default states. the default state represents the minimum functionality feature set required to successfully bring up the system. hence, it does not represent the optimal system configuration. it is the responsibility of the system initialization software (usually bios) to properly determine the dram configura- tions, cache configuration, operating parameters and optional system features that are applicable, and to program the pcmc registers accordingly. 30
82434LX/82434nx the following nomenclature is used for access attributes. ro read only. if a register is read only, writes to this register have no effect. r/w read/write. a register with this attribute can be read and written. r/wc read/write clear. a register bit with this attribute can be read and written. however, a write of a 1 clears (sets to 0) the corresponding bit and a write of a 0 has no effect. 3.1 i/o mapped registers the 82434LX pcmc contains three registers that reside in the cpu i/o address spaceethe configuration space enable (cse) register, the turbo-reset control (trc) register and the forward (forw) register. these registers can not reside in pci configuration space because of the special functions they perform. the cse register enables/disables the configuration space and, hence, can not reside in that space. the trc register enables/disables deturbo mode which effectively slows the processor to accommodate software programs that rely on the slow speed of pc/xt systems to time certain events. the forw register deter- mines which of the possible hierarchical pci buses a cycle is directed. the 82434LX uses mechanism y 2 for accessing pci configuration space. the 82434nx pcmc contains five registers that reside in the cpu i/o address spacethe configuration ad- dress (confadd) register, the configuration space enable (cse) register, the turbo-reset control (trc) register, the forward (forw) register, and the pci mechanism control (pmc) register. the cse, trc, and forw registers are the same for both the 82434LX and 82434nx pcmcs. the 82434nx can use either configuration access mechanism y 1or y 2 for accessing pci configuration space. when configuration ac- cess mechanism y 1 is used (see section 3.2, pci configuration space mapped registers), the confadd register enables/disables the configuration space and determines what portion of configuration space is visible through the configuration data (confdata) window. the cse and forw registers are used for configuration access mechanism y 2. the pci mechanism control (pmc) register selects whether configura- tion access mechanism 1 or 2 is used (see the rev 2.0 pci local bus specification). 3.1.1 confaddeconfiguration address register i/o address: 0cf8h accessed as a dword default value: 00000000h access: read/write size: 32 bits confadd is a 32-bit register used in configuration access mechanism y 1. it is accessed only when refer- enced as a dword and pcams in the pmc register is set to 1. byte or word references ``pass through'' the confadd register to the i/o locations ``behind'' it. for example a byte access to 0cf8h will access the cse register, while a word access to cf8h will access both the cse and trc registers. the confadd register contains the bus number, device number, function number, and register number where the confdata window is located. 31
82434LX/82434nx bit description 31 configuration enable (cone)er/w: when cone e 1, accesses to pci configuration space are enabled, if the pcams bit of the pmc register is also 1. when cone e 0, accesses to pci configuration space are disabled, if the pcams bit is 1. if the pcams bit is 0, this bit has no effect. 30:24 reserved 23:16 bus number (busnum)er/w: when the busnum is programmed to 00h, the target of the configuration cycle is either the pcmc or the pci local bus that is directly connected to the pcmc. pci access mechanism y 1 can generate either type 0 or type 1 configuration cycles on pci. a type 0 configuration cycle is generated on pci if the bus number is programmed to 00h and the pcmc is not the target. if the bus number is non-zero a type 1 configuration cycle is generated on pci with the bus number mapped to ad [ 23:16 ] during the address phase. 15:11 device number (devnum)er/w: this field selects one agent on the pci bus selected by the bus number. during a type 1 configuration cycle this field is mapped to ad [ 15:11 ] . during a type 0 configuration cycle this field is decoded and one of ad [ 31:17 ] is driven to a 1. the pcmc is always device number 0. 10:8 function number (funcnum)er/w: this field is mapped to ad [ 10:8 ] during pci configuration cycles. this allows the configuration registers of a particular function in a multi- function device to be accessed. 7:2 register number (regnum)er/w: this field selects one register within a particular bus, device, and function as specified by the other fields in the configuration address register. regnum is mapped to ad [ 7:2 ] during pci configuration cycles. 1:0 reserved 3.1.2 cseeconfiguration space enable register i/o address: 0cf8h default value: 00h attribute: read/write size: 8 bits the cse register enables/disables configuration space access and provides access to specific functions within a pci agent. the register is located in the cpu i/o address space. the pcmc, as a host/pci bridge, supports multi-function devices on the pci bus. the function number permits individual configuration spaces for up to eight functions within an agent. the register is located in the cpu i/o address space. bit description 7:4 key field (key)er/w: this field is used only when the pci mechanism control register (pmc) indicates configuration access mechanism 2 is to be used. when the key field is programmed to 0h, the pci configuration space is disabled. when the key field is programmed to a non-zero value, all cpu accesses to cnxxh (where n is a non zero value) are forwarded to pci as configuration space accesses. additionally, when the key field is programmed to a non-zero value, all cpu accesses to c0xxh are intercepted by the pcmc and directed to a pcmc internal register. 3:1 function number (fn)er/w: for multi-function devices, this field selects a particular function within a pci device. during a configuration cycle, bits [ 3:1 ] become part of the pci bus address and correspond to ad [ 10:8 ] . 0 reserved 32
82434LX/82434nx 3.1.3 trceturbo-reset control register i/o address: 0cf9h default value: 00h attribute: read/write size: 8 bits the trc register is an 8-bit read/write register that selects turbo/deturbo mode of the cpu, initiates pci bus and cpu reset cycles, and initiates the cpu built in self test (bist). trc is located in cpu i/o address space. bit description 7:3 reserved 2 reset cpu (rcpu)er/w: rcpu is used to initiate a hard reset or soft reset to the cpu. during a hard reset, the pcmc asserts cpurst and pcirst y . the pcmc initiates a hard reset when this register is programmed for a hard reset or when the pwrok signal is asserted. during a soft reset, the pcmc asserts init. the pcmc initiates a soft reset when this register is programmed for a soft reset and in response to a shutdown special cycle. note that a hard reset initializes the entire system and invalidates the cpu cache. a soft reset initializes only the cpu. the contents of the cpu cache are unaffected. this bit is used in conjunction with bit 1 of this register. bit 1 must be set up prior to writin ga1to this register. thus, two write operations are required to initiate a reset using this bit. the first write operation programs bit 1 to the appropriate state while setting this bit to 0. the second write operation keeps bit 1 at the programmed state (1 or 0) while setting this bit to a 1. when rcpu transitions from a 0 to a 1, a hard reset is initiated if bit 1 e 1 and a soft reset is initiated if bit 1 e 0. 1 system hard reset enable (shre)er/w: this bit is used in conjunction with bit 2 of this register to initiate either a hard or soft reset. when shre e 1, the pcmc initiates a hard reset to the cpu when bit 2 transitions from 0 to 1. when shre e 0, the pcmc initiates a soft reset when bit 2 transitions from 0 to 1. 0 deturbo mode (dm)er/w: this bit enables and disables deturbo mode. when dm e 1, the pcmc is in the deturbo mode. in this mode, the pcmc periodically asserts the ahold signal to slow down the effective speed of the cpu. the ahold duty cycle is programmable through the deturbo frequency control (dfc) register. when dm e 0, the deturbo mode is disabled. deturbo mode can be used to maintain backward compatibility with older software packages that rely on the operating speed of older processors. for accurate speed emulation, caching should be disabled. if caching is disabled during runtime, the following steps should be performed to make sure that modified lines have been flushed from the cache to main memory before entering deturbo mode. disable the primary cache via the pce bit in the hcs register. this prevents the ken y signal from being asserted, which prevents any further first and second level cache line fills. at this point, software executes the wbinvd instruction to flush the caches, and then sets dm to 1. when exiting the deturbo mode, the system software must first set dm to 0, then enable first and second level caching by writing to the hcs register. 33
82434LX/82434nx 3.1.4 forweforward register i/o address: 0cfah default value: 00h attribute: read/write size: 8 bits this 8-bit register specifies which pci bus configuration space is enabled in a multiple pci bus configuration. the default value for the forw register enables the configuration space of the pci bus connected to the pcmc. bit description 7:0 forward bus numberer/w: when this register value is 00h, the configuration space of the pci bus connected to the pcmc is enabled and the pcmc initiates a type 0 configuration cycle. if the value of this register is not 00h, the pcmc initiates a type 1 configuration cycle to forward the cycle (via one or more pci/pci bridges) to the pci bus specified by the contents of this register. for non- zero values, bits [ 7:0 ] are mapped to ad [ 23:16 ] , respectively. 3.1.5 pmcepci mechanism control register i/o address: 0cfbh default value: 00h access: read/write size: 8 bits the pmc register selects whether pci configuration access mechanism 1 or 2 is to be used. the register is located in the cpu i/o address space. bit description 7:1 reserved 0 pci configuration access mechanism select (pcams)er/w: when pcams e 0, the pcmc uses to pci configuration access mechanism y 2. when pcams e 1, the pcmc uses to pci configuration access mechanism y 1. the confadd and confdata registers are only accessible when pcams e 1. 3.1.6 confdataeconfiguration data register i/o address: 0cfch default value: 00h access: read/write size: 32 bits confdata is a 32 bit read/write window into configuration space. the portion of configuration space that is referenced by confdata is determined by the contents of confadd. bit description 31:0 configuration data window (cdw)er/w: when using configuration access mechanism y 1 if bit 31 of confadd is 1 any i/o reference that falls in the confdata i/o space will be mapped to configuration space using the contents of confadd. 34
82434LX/82434nx 3.2 pci configuration space mapped registers the pci bus defines a slot based ``configuration space'' that allows each device to contain up to 256 8-bit configuration registers. the pci specification defines two bus cycles to access the pci configuration spacee configuration read and configuration write . while memory and i/o spaces are supported by the pentium processor, configuration space is not supported. for pci configuration space access, the pcmc translates the pentium processor i/o cycles into pci configuration cycles. table 1 shows the pcmc configuration space. table 1. pcmc configuration space address register register name access offset symbol 00 01h vid vendor identification ro 02 03h did device identification ro 04 05h pcicmd command register r/w 06 07h pcists status register ro, r/wc 08h rid revision identification ro 09h rlpi register-level programming interface ro 0ah sccd sub-class code ro 0bh bccd base class code ro 0ch e reserved e 0dh mlt master latency timer r/w 0eh e reserved e 0fh bist bist register ro 10 4fh e reserved e 50h hcs host cpu selection r/w 51h dfc deturbo frequency control r/w 52h scc secondary cache control r/w 53h hbc host read/write buffer control r/w 54h pbc pci read/write buffer control r/w 55h e reserved e 56h e reserved e 57h dramc dram control r/w 58h dramt dram timing r/w 59 5fh pam [ 6:0 ] programmable attribute map (7 registers) r/w 60 65h drb [ 5:0 ] dram row boundary (6 registers) r/w 66 67h drb [ 7:6 ] dram row boundary (2 registers) r/w 68 6bh drbe dram row boundary extension r/w 6c 6fh e reserved e 70h errcmd error command r/w 35
82434LX/82434nx table 1. pcmc configuration space (continued) address register register name access offset symbol 71h errsts error status r/wc 72h smrs smram space control r/w 73 77h e reserved e 78 79h msg memory space gap r/w 7a 7b e reserved e 7c 7fh fbr frame buffer range r/w 80 ffh e reserved e note: shaded rows indicate register differences between the 82434LX and 82434nx devices. for non-shaded rows, the registers are the same for the two devices. 3.2.1 configuration space access mechanism the 82434LX supports configuration space access mechanism y 2 and the 82434nx supports both configu- ration space access mechanisms y 1 and y 2. the mechanism is selected via the pcams bit in the pmc register. the bus cycles used to access pcmc internal configuration registers are described in section 7.0, pci interface. 3.2.1.1 access mechanism y 1: for configuration access mechanism y 1, the 82434nx pcmc uses the confadd and confdata regis- ters. note that while the confadd and pmc register address spaces overlap, the confadd register is referenced only by a dword read or write to cf8h. this allows the pmc register to be accessed by a byte write to cfbh, even when using configuration access mechanism y 1. to reference a configuration register with access mechanism y 1, a dword i/o write loads the confadd register with a 32-bit value that specifies the pci bus, the device on that bus, the function within the device, and a specific configuration register of the device function being accessed (figure 4). bit 31 of the confadd register must be 1 to enable a configuration cycle. confdata then becomes a four byte window of configu- ration space specified by the contents of the confadd register. a read or write to confdata results in the pcmc translating confadd into a pci configuration cycle. type 0 access if the busnum field is 0, a type 0 configuration cycle is performed on the pci. bus confadd [ 10:2 ] are mapped directly to ad [ 10:2 ] . the devnum field is decoded onto ad [ 31:17 ] and ad [ 15:11 ] (for accesses to device 1, ad17 is asserted; for accesses to device y 2, ad18 is asserted; etc.). the pcmc is device y 0 and does not pass its configuration cycles to the pci bus. thus, ad16 is never asserted. for accesses to device 15, ad31 is asserted, etc. this mapping allows the same device number to activate the same ad line in either configuration access mechanism. all other ad lines are 0. 36
82434LX/82434nx 290479 5 figure 4. mechanism y 1 type 0 configuration address to pci address mapping type 1 access if the busnum field of the confadd register is non-zero, a type 1 configuration cycle is performed on the pci bus. confadd [ 23:2 ] are mapped directly to ad [ 23:2 ] (figure 5). ad [ 1:0 ] are driven to 01 to indicate a type 1 configuration cycle. all other lines are driven to 0. 290479 6 figure 5. mechanism y 1 type 1 configuration address to pci address mapping 3.2.1.2 access mechanism y 2 the 82434LX/82434nx pcmc uses the cse and forward registers for configuration access mechanism y 2. when pci configuration space is enabled via the cse register, the pcmc maps pci configuration space into 4-kbytes of cpu i/o space. each pci device has its own 256-byte configuration space. when configuration space is enabled, cpu accesses to i/o locations cxxxh are translated into configuration space accesses. in this mode, the pcmc translates all i/o cycles in the c100h cfffh range into configuration cycles on the pci bus. i/o accesses within the c000h c0ffh range are intercepted by the pcmc and are directed to the pcmc internal configuration registers. these cycles are not forwarded to the pci bus. when configuration space access is disabled, cpu accesses to i/o locations cxxxh are forwarded to the pci bus i/o space. cpu cycles to i/o locations other than cxxxh are unaffected by whether the configuration mode is enabled or disabled. these cycles are always treated as ordinary i/o cycles by the pcmc. 37
82434LX/82434nx type 0 access if the forward register contains 00h a type 0 configuration access is generated on the pci bus (figure 6). for type 0 configuration cycles, ad [ 1:0 ] e 00. host cpu address bits a [ 7:2 ] are not translated and become ad [ 7:2 ] on the pci bus. ad [ 7:2 ] select one of the 256 8-bit i/o locations in the pci configuration space. the function number field from the cse register (cse [ 3:1 ] ) is driven on ad [ 10:8 ] . host cpu address bits a [ 11:8 ] are mapped to an idsel input for each of the 16 possible pci devices. the idsel input for each pci device must be hard-wired to one of the ad [ 31:16 ] signals on the pci bus. ad16 is reserved for the pcmc. when cpu address a [ 11:8 ] e fh, pci address bits a31 e 1 and a [ 30:16 ] e 00h. other devices on the pci bus should not use ad16. note that when a [ 11:8 ] e 0h, an access to the pcmc internal registers occurs and the cycle is not forwarded to the pci bus. 290479 7 figure 6. mechanism y 2 type 0 host-to-pci address mapping 38
82434LX/82434nx type 1 access if the forward register is non-zero a type 1 configuration access is generated on pci. for type 1 configuration cycles, ad [ 1:0 ] e 01. ad [ 10:2 ] are generated the same as for the type 0 configuration cycle. host cpu address bits a [ 11:8 ] contain the specific device number and are mapped to ad [ 14:11 ] .ad [ 23:16 ] contain the bus number of the pci bus that is to be accessed and corresponds to the forward address register bits [ 7:0 ] . during a type 1 configuration access ad [ 1:0 ] e 01 (figure 7). the register index and function number are mapped to the ad lines the same way in type 1 configuration access as in a type 0 configuration access. cpu address bits a [ 11:8 ] are mapped directly to pci lines ad [ 14:11 ] as the device number. the contents of the forward register are mapped to ad [ 23:16 ] to form the bus number. 290479 8 figure 7. mechanism y 2 type 1 host-to-pci address mapping 39
82434LX/82434nx 3.2.2 videvendor identification register address offset: 00 01h default value: 8086h attribute: read only size: 16 bits the vid register contains the vendor identification number. this 16-bit register combined with the device identification register uniquely identify any pci device. writes to this register have no effect. bits description 15:0 vendor identification number: this is a 16-bit value assigned to intel. 3.2.3 didedevice identification register address offset: 02 03h default value: 04a3h attribute: read only size: 16 bits this 16-bit register combined with the vendor identification register uniquely identifies any pci device. writes to this register have no effect. bits description 15:0 device identification number: this is a 16 bit value assigned to the pcmc. 40
82434LX/82434nx 3.2.4 pcicmdepci command register address offset: 04 05h default: 06h attribute: read/write size: 16 bits this 16-bit register provides basic control over the pcmc's ability to respond to pci cycles. the pcicmd register enables and disables the serr y signal, the parity error signal (perr y ), pcmc response to pci special cycles, and enables and disables pci master accesses to main memory. bits description 15:9 reserved 8 serr y enable (serre): serre enables/disables the serr y signal. when serre e 1 and perre e 1, serr y is asserted if the pcmc detects a pci bus address/data parity error, or main memory (dram) or cache parity error, and the corresponding errors are enabled in the error- command register. when serre e 1 and bit 7 in the error command register is set to 1, the pcmc asserts serr y when it detects a target abort on a pcmc-initiated pci cycle. when serre e 0, serr y is never asserted. 7 reserved 6 parity error enable (perre): perre controls the pcmc's response to pci parity errors. this bit is a master enable for bit 3 of the errcmd register. perre works in conjunction with the serre bit to enable serr y assertion when the pcmc detects a pci bus parity error, or a main memory or cache parity error. 5:3 reserved 2 bus master enable (bme): the pcmc does not support disabling of its bus master capability on the pci bus. this bit is always set to 1, permitting the pcmc to function as a pci bus master. writes to this bit position have no affect. 1 memory access enable (mae): this bit enables/disables pci master access to main memory (dram). when mae e 1, the pcmc permits pci masters to access main memory if the memcs y signal is asserted. when mae e 0, the pcmc does not respond to pci master main memory accesses (memcs y asserted). 0 i/o access enable (ioae): the pcmc does not respond to pci i/o cycles, hence this command is not supported. pci master access to i/o space on the host bus is always disabled. 41
82434LX/82434nx 3.2.5 pcistsepci status register address offset: 06 07h default value: 40h attribute: read only, read/write clear size: 16 bits pcists is a 16-bit status register that reports the occurrence of a pci master abort, pci target abort, and dram or cache parity error. pcists also indicates the devsel y timing that has been set by the pcmc hardware. bits [ 15:12 ] are read/write clear and bits [ 10:9 ] are read only. bits attribute description 15 reserved 14 r/wc signaled system error (sse): when the pcmc asserts the serr y signal, this bit is also set to 1. software sets sse to 0 by writin ga1to this bit. 13 r/wc received master abort status (rmas): when the pcmc terminates a host-to- pci transaction (pcmc is a pci master), which is not a special cycle, with a master abort, this bit is set to 1. software resets this bit to 0 by writin ga1toit. 12 r/wc received target abort status (rtas): when a pcmc-initiated pci transaction is terminated with a target abort, rtas is set to 1. the pcmc also asserts serr y if the serr y target abort bit in the errcmd register is 1. software resets rtas to 0 by writin ga1toit. 11 reserved 10:9 ro devsel y timing (devt): this 2-bit field indicates the timing of the devsel y signal when the pcmc responds as a target. the pci specification defines three allowable timings for assertion of devsel y :00 e fast, 01 e medium, and 10 e slow (devt e 11 is reserved). devt indicates the slowest time that a device asserts devsel y for any bus command, except configuration read and write cycles. note that these two bits determine the slowest time that the pcmc asserts devsel y . however, the pcmc can also assert devsel y in medium time. the pcmc asserts devsel y in response to sampling memcs y asserted. the pcmc samples memcs y one and two clocks after frame y is asserted. if memcs y is asserted one pci clock after frame y is asserted, then the pcmc responds with devsel y in slow time. 8 r/wc data parity detected (dpd): this bit is set to 1 when all of the following conditions are met: 1). the pcmc asserted perr y or sampled perr y asserted. 2). the pcmc was the bus master for the operation in which the error occurred. 3). the perre bit in the command register is set to 1. software resets dpd to 0 by writin ga1toit. 7:0 reserved 42
82434LX/82434nx 3.2.6 riderevision identification register address offset: 08h default value: 03h for a 3 stepping (82434LX) 01h for a 1 stepping (82434LX) 10h for a 0 stepping (82434nx) 11h for a 1 stepping (82434nx) attribute: read only size: 8 bits this register contains the revision number of the pcmc. these bits are read only and writes to this register have no effect. for the a 2 stepping of the 82434LX, this value is 03h. for the a 1 stepping of the 82434nx, this value is 11h. bits description 7:0 revision identification number: this is an 8-bit value that indicates the revision identification number for the pcmc. 3.2.7 rlpieregister-level programming interface register address offset: 09h default value: 00h attribute: read only size: 8 bits this register defines the pcmc as having no defined register-level programming interface. bits description 7:0 register-level programming interface (rlpi): the value of 00h defines the pcmc as having no defined register-level programming interface. 3.2.8 subcesub-class code register address offset: 0ah default value: 00h attribute: read only size: 8 bits this register defines the pcmc as a host bridge. bits description 7:0 sub-class code (sccd): the value of this register is 00h defining the pcmc as host bridge. 43
82434LX/82434nx 3.2.9 basecebase class code register address offset: 0bh default value: 06h attribute: read only size: 8 bits this register defines the pcmc as a bridge device. bits description 7:0 base class code (bccd): the value in this register is 06h defining the pcmc as bridge device. 3.2.10 mltemaster latency timer register address offset: 0dh default value: 20h attribute: read/write size: 8 bits mlt is an 8-bit register that controls the amount of time the pcmc, as a bus master, can burst data on the pci bus. mlt is used when the pcmc becomes the pci bus master and is cleared and suspended when the pcmc is not asserting frame y . when the pcmc asserts frame y , the counter is enabled and begins counting. if the pcmc finishes its transaction before the count expires, the mlt count is ignored. if the count expires before the transaction completes, the pcmc initiates a transaction termination as soon as its gnt y is removed. the number of clocks programmed in the mlt represents the guaranteed time slice (measured in pci clocks) allotted to the pcmc, after which it must surrender the bus as soon as its gnt y is taken away. the number of clocks in the master latency timer is the count value field multiplied by 16. bits description 7:4 master latency timer count value: if gnt y is negated after the burst cycle is initiated, the pcmc limits the duration of the burst cycle to the number of pci bus clocks specified by this field multiplied by 16. 3:0 reserved 3.2.11 bistebist register address offset: 0fh default value: 0h attribute: read only size: 8 bits the bist function is not supported by the pcmc. writes to this register have no affect. bits attribute description 7ro bist supported: this read only bit is always set to 0, disabling the bist function. writes to this bit position have no affect. 6rw start bist: this function is not supported and writes have no affect. 5:4 reserved 3:0 ro completion code: this read only field always returns 0 when read and writes have no affect. 44
82434LX/82434nx 3.2.12 hcsehost cpu selection register address offset: 50h default value: 82h (82434LX) a2h (83434nx) access: read/write, read only size: 8 bits the hcs register is used to specify the host cpu type and speed. this 8-bit register is also used to enable and disable the first level cache. bits access description 7:5 ro host cpu type (hct): this field defines the host cpu type. 82434LX these bits are hardwired to 100 which selects the pentium processor. all other combinations are reserved. 82434nx in the 82434nx, these bits are reserved. reads and writes to these bits have no effect. 4:3 reserved 2 r/w first level cache enable (flce): flce enables and disables the first level cache. when flce e 1, the pcmc responds to cpu cycles with ken y asserted for cacheable memory cycles. when flce e 0, ken y is always negated. this prevents new cache line fills to either the first level or second level caches. 1:0 r/w host operating frequency (hof): the dram refresh rate is adjusted according to the frequency selected by this field. for the 82434LX, only bit 0 is used and bit 1 is reserved. 82434LX bit 1 is reserved. if bit 0 is 1, the 82434LX supports a 66 mhz cpu. if bit 0 is 0, the 82434LX supports a 60 mhz cpu. 82434nx these bits select the host cpu frequency supported as follows: bits [ 1:0 ] host cpu frequency 00 reserved 01 50 mhz 10 60 mhz 11 66 mhz 45
82434LX/82434nx 3.2.13 dfcedeturbo frequency control register address offset: 51h default value: 80h attribute: read/write size: 8 bits some software packages rely on the operating speed of the processor to time certain system events. to maintain backward compatibility with these software packages, the pcmc provides a mechanism to emulate a slower operating speed. this emulation is achieved with the pcmc's deturbo mode. the deturbo mode is enabled and disabled via the dm bit in the turbo-reset control register. when the deturbo mode is enabled, the pcmc periodically asserts ahold to slow down the effective speed of the cpu. the duty cycle of the ahold active period is controlled by the dfc register. bits description 7:6 deturbo mode frequency adjustment value: this 8-bit value effectively defines the duty cycle of the ahold signal. dfc [ 7:6 ] are programmable and dfc [ 5:0 ] are 0. the value programmed into this register is compared against a free running 8-bit counter running at (/8 the cpu clock. when the counter is greater than the value specified in this register, ahold is asserted. ahold is negated when the counter value is equal to or smaller than the contents of this register. ahold is negated when the counter rolls over to 00h. the deturbo emulation speed is directly proportional to the value in this register. smaller values in this register yield slower deturbo emulation speed. the value of 00h is reserved. 5:0 reserved 3.2.14 sccesecondary cache control register address offset: 52h default value: sss01r10 (82434LX) sss01010 (82434nx) (s e strapping option) attribute: read/write size: 8 bits this 8-bit register defines the secondary cache operations. the scc register enables and disables the second level cache, adjusts cache size, selects the cache write policy, and defines the cache sram type. after hard reset, scc [ 7:5 ] contain the opposite of the signal levels sampled on the host address lines a [ 31:29 ] . bits description 7:6 secondary cache size (scs): this field defines the size of the second level cache. the values sampled on the a [ 31:30 ] lines at the rising edge of the pwrok signal are inverted and stored in this field. bits [ 7:6 ] secondary cache size 00 cache not populated 01 reserved 10 256-kbytes 11 512-kbytes 46
82434LX/82434nx bits description 5 sram type (sramt): this bit selects between standard srams or burst srams to implement the second level cache. when sramt e 0, standard srams are selected. when sramt e 1, burst srams are selected. this bit reflects the signal level on the a29 pin at the rising edge of the pwrok signal. this value can be overwritten with subsequent writes to the scc register. 4 82434LX: secondary cache allocation (sca): sca controls when the pcmc performs line fills in the second level cache. when sca is set to 0, only cpu reads of cacheable main memory with cache y asserted are cached in the second level cache. when sca is set to 1, all cpu reads of cacheable main memory are cached in the second level cache. 3 cache byte control (cbc): when programmed for asynchronous srams, this bit defines whether the cache uses individual write enables per byte or has a single write enable and byte select lines per byte. when cbc is set to 1, write enable control is used. when cbc is set to 0, byte select control is used. 2 82434LX: reserved 82434nx: sram connectivity (sramc): this bit enables different connectivities for the second level cache. when sramc is set to 0, the second level cache is in 82434LX compatible mode and all connections between the pcmc and second level cache srams are the same as the 82434LX. when asynchronous srams are used, setting this bit to 1 enables the ccs [ 1:0 ] y functionality. ccs [ 1:0 ] y are used with asynchronous srams to de-select the srams, placing them in a low power standby mode. when the cpu runs a halt or stop grant special cycle, the 82434nx negates ccs [ 1:0 ] y , placing the second level cache in a power saving mode. the pcmc then asserts ccs [ 1:0 ] y (activating the srams) when the cpu asserts ads y . when using burst srams, setting this bit to 1 enables the ccs1 y functionality and indicates to the pcmc that no external address latch is present. 1 82434LX: secondary cache write policy (scwp): scwp selects between write-back and write-through cache policies for the second level cache. when scwp e 0 and the second level cache is enabled (bit 0 e 1), the second level cache is configured for write-through mode. when scwp e 1 and the second level cache is enabled (bit 0 e 1), the second level cache is configured for write-back mode. 82434nx: reserved: secondary cache write-through mode is not supported. the secondary cache is always in write-back mode and this bit has no affect. scwp can be set to 0, however, the 82434nx will still operate the secondary cache in write-back mode. 0 secondary cache enable (sce): sce enables and disables the secondary cache. when sce e 1, the secondary cache is enabled. when sce e 0, the secondary cache is disabled. when the secondary cache is disabled, the pcmc forwards all main memory cycles to the dram interface. note that setting this bit to 0 does not affect existing valid cache lines. if a cache line contains modified data, the data is not written back to memory. valid lines in the cache remain valid. when the secondary cache is disabled, the cwe [ 7:0 ] y lines remain negated. coe [ 1:0 ] y may still toggle. when system software disables secondary caching through this register during run-time, the software should first flush the second level cache. this process is accomplished by first disabling first level caching via the pce bit in the hcs register. this prevents the ken y signal from being asserted, which disables any further line fills. at this point, software executes the wbinvd instruction to flush the caches. when the instruction completes, bit 0 of this register can be reset to 0, disabling the secondary cache. the first level cache can then be enabled by writing the pce bit in the hcs register. 47
82434LX/82434nx 3.2.15 hbcehost read/write buffer control address offset: 53h default value: 00h attribute: read/write size: 8 bits the hbc register enables and disables host-to-main memory and host-to-pci posting of write cycles. when posting is enabled, the write buffers in the lbx devices post the data that is destined for either main memory or pci. this register also permits a cpu-to-main memory read cycle to be performed before any pending posted write data is written to memory. bits description 7:4 reserved 3 read-around-write enable (rawcm): if enabled, the pcmc, during a cpu read cycle to memory where posted write cycles are pending, internally snoops the write buffers. if the address of the read differs from the posted write addresses, the pcmc initiates the memory read cycle ahead of the pending posted memory write. when rawcm e 0, the pending posted write is written to memory before the memory read is performed. when rawcm e 1, the pcmc initiates the memory read ahead of the pending posted memory writes. 2 reserved 1 host-to-pci posting enable (hppe): this bit enables/disables the posting of host-to-pci write data in the lbx posting buffers. when hppe e 1, up to 4 dwords of data can be posted to pci. hppe e 0 is reserved. buffering is disabled and each cpu write does not complete until the pci transaction completes (trdy y is asserted). 0 82434LX: host-to-memory posting enable (hmpe): this bit enables/disables the posting of host-to-main memory write data in the lbx buffers. when hmpe e 1, the cpu can post a single write or a burst write (4 qwords). the cpu burst write completes at 4-1-1-1 when the second level cache is in write-back mode and at 3-1-1-1 when the second level cache is either disabled or in write-through mode. when hmpe e 0, host-to-main memory posting is disabled and the cpu write cycles do not complete until the data is written to memory. 82434nx: reserved: for the 82434nx, posting is always enabled and this bit has no affect. the cpu can post a single write or burst write (4 qwords). hmpe can be set to 0, however, the 82434nx will still allow posting of cpu-to-main memory writes. 48
82434LX/82434nx 3.2.16 pbcepci read/write buffer control register address offset: 54h default value: 00h attribute: read/write size: 8 bits the pbc register enables and disables pci-to-main memory write posting and permits single cpu-to-pci writes to be assembled into pci burst cycles. bits description 7:3 reserved 2 lbxs connected to trdy y : the trdy y pin on the lbxs can be connected either to the pci trdy y signal or to ground. the cycle time for cpu-to-pci writes is improved if trdy y is connected to the lbxs. since there are two lbxs used in a system, connecting this signal to the lbxs increases the electrical loading of trdy y by two loads. when the lbxs are externally hard-wired to trdy y , this bit should be set to 1. note that this should be done prior to the first host-to-pci write or data corruption will occur. setting this bit to 1 enables the capability of cpu-to-pci writes at 2-1-1- 1... (pci clocks). when this bit is 0, the lbxs are not connected to trdy y and cpu-to-pci writes are completed at 2-2-2- 2... timing. 1 pci burst write enable (pbwe): this bit enables and disables pci burst memory write cycles for back-to-back sequential cpu memory write cycles to pci. when pbwe is set to 1, pci burst writes are enabled. when pbwe is reset to 0, pci burst writes are disabled and each single cpu write to pci invokes a single pci write cycle (each cycle has an associated frame y sequence). 0 pci-to-memory posting enable (pmpe): this bit enables and disables posting of pci-to- memory write cycles. the posting occurs in a pair of four dword-deep buffers in the lbxs. when pmpe is set to 1, these buffers are used to post pci-to-main memory write data. when pmpe is reset to 0, pci write transactions to main memory are limited to single transfers. the pcmc asserts stop y with the first trdy y to disconnect the pci master. 49
82434LX/82434nx 3.2.17 dramcedram control register address offset: 57h default value: 31h attribute: read/write size: 8 bits this 8-bit register controls main memory dram operating modes and features. bits description 7:6 82434LX: reserved 82434nx: dram burst timing (dbt): the dram interface can be configured for 3 different burst timings. the cas y pulse width for x-3-3-3 timing is one clock shorter than the cas y pulse width for x-4-4-4 timing. bits [ 7:6 ] burst timing 0 0 x-4-4-4 read/write timing (default) 0 1 x-4-4-4 read, x-3-3-3 write timing 1 0 reserved 1 1 x-3-3-3 read/write timing 5 parity error mask (perrm): when perrm e 1, parity errors generated during dram read cycles initiated by either the cpu request or a pci master are masked. this bit affects bits 0 and 1 of the error command register and the ability of the pcmc to respond to pchk y and assert serr y when a dram parity error occurs. when perrm is reset to 0, parity errors are not masked. 4 0-active ras y mode: this bit determines if the dram page for a particular row remains open (i.e. ras y remains asserted after a dram cycle) enabling the possibility that the next dram access may be either a page hit, a page miss, or a row miss. the dram interface is then in 1-active ras y mode. if this bit is reset to 0, ras y remains asserted after a dram cycle. if this bit is set to 1, ras y is negated after every dram cycle, resulting in a row miss for every dram cycle. the dram interface is then in 0-active ras y mode. 3 smram enable (smre): when smre e 1, cpu accesses to smm space are qualified with the smiact y pin of the cpu. the location of this space is determined by the sbs field of the smram register. read and write cycles to smm space function normally if smiact y is asserted. if smiact y is negated when accessing this space, the cycle is forwarded to pci. when smre e 0, accesses to smm space are treated normally and smiact y has no effect. smre must be set to 1 to enable the use of the smram register at configuration space offset 72h. 2 burst of four refresh (bfr): when bfr is set to 1, refreshes are performed in sets of four, at a frequency (/4 of the normal refresh rate. the pcmc defers refreshes to idle times, if possible. when bfr is reset to 0, single refreshes occur at 15.6 m s refresh rate. 1 82434LX: refresh type (rt): when rt e 1, the pcmc uses cas y -before-ras y timing to refresh the dram array. for this refresh type, the pcmc does not supply refresh addresses. when rt e 0, ras y only refresh is used and the pcmc drives refresh addresses on the ma [ 10:0 ] lines. ras y only refresh can be used with any type of second level cache configuration (i.e., no second level cache is present, or either a burst sram or standard sram second level cache is implemented). cas y -before-ras y refresh should not be used when a standard sram second level cache is implemented. 82434nx: refresh type (rt): in addition to above, when rt e 0, ras y only refresh is used and the pcmc drives refresh addresses on the ma [ 11:0 ] lines. also, cas y -before-ras y refresh can be used with a standrad sram second level cache. 0 refresh enable (re): when re is set to 1, the main memory array is refreshed as configured via bits 1 and 2 of this register. when re is reset to 0, dram refresh is disabled. note that disabling refresh results in the loss of dram data. 50
82434LX/82434nx 3.2.18 dramtedram timing register address offset: 58h default value: 00h attribute: read/write size: 8 bits for the 82434LX, this register controls the leadoff latency for cpu dram accesses. for the 82434nx, this register provides additional control over dram timings. one additional wait-state can be independently added before the assertion of ras y , the assertion of the first cas y , or both. this is to allow more flexibility in the layout of the motherboard and in the selection of dram speed grades. bits description 7:2 reserved 1 82434LX: reserved 82434nx: ras y wait-state (rws): when rws e 1, one additional wait state will be inserted before ras y is asserted for row misses or page misses in 1-active ras mode and all cycles in 0-active ras mode. this provides additional ma [ 11:0 ] setup time to ras y assertion. 0 cas y wait-state (cws): when cws e 1, one additional wait state will be inserted before the first assertion of cas y within a burst cycle. there is no additional delay between cas y assertions. this provides additional ma [ 11:0 ] setup time to cas y assertion. the cws bit is typically reset to 0 for 60 mhz operation and set to 1 for 66 mhz operation. 3.2.19 pameprogrammable attribute map registers (pam [ 6:0 ] ) address offset: 59 5fh default value: pam0 e 0fh, pam [ 1:6 ] e 00h attribute: read/write the pcmc allows programmable memory and cacheability attributes on 14 memory segments of various sizes in the 512 kbyte 1 mbyte address range. seven programmable attribute map (pam) registers are used to support these features. three bits are used to specify cacheability and memory attributes for each memory segment. these attributes are: re: read enable. when re e 1, the cpu read accesses to the corresponding memory segment are direct- ed to main memory. conversely, when re e 0, the cpu read accesses are directed to pci. we: write enable. when we e 1, the cpu write accesses to the corresponding memory segment are directed to main memory. conversely, when we e 0, the cpu write accesses are directed to pci. ce: cache enable. when ce e 1, the corresponding memory segment is cacheable. ce must not be set to 1 when re is reset to 0 for any particular memory segment. when ce e 1 and we e 0, the correspond- ing memory segment is cached in the first and second level caches only on cpu coded read cycles. the re and we attributes permit a memory segment to be read only, write only, read/write, or disabled. for example, if a memory segment has re e 1 and we e 0, the segment is read only. the characteristics for memory segments with these read/write attributes are described in table 2. 51
82434LX/82434nx table 2. attribute definition read/write definition attribute read only read cycles: cpu cycles are serviced by the dram in a normal manner. write cycles: cpu initiated write cycles are ignored by the dram interface as well as the cache. instead, the cycles are passed to pci for termination. areas marked as read only are cacheable for code accesses only. these regions may be cached in the second level cache, however as noted above, writes are forwarded to pci, effectively write protecting the data. write only read cycles: all read cycles are ignored by the dram interface as well as the second level cache. cpu-initiated read cycles are passed onto pci for termination. the write only state can be used while copying the contents of a rom, accessible on pci, to main memory for shadowing, as in the case of bios shadowing. write cycles: cpu write cycles are serviced by the dram and cache in a normal manner. read/write this is the normal operating mode of main memory. both read and write cycles from the cpu and pci are serviced by the dram and cache interface. disabled all read and write cycles to this area are ignored by the dram and cache interface. these cycles are forwarded to pci for termination. each pam register controls two regions, typically 16-kbyte in size. each of these regions have a 4-bit field. the four bits that control each region have the same encoding and are defined in table 3. table 3. attribute bit assignment bits [ 7,3 ] bits [ 6,2 ] bits [ 5,1 ] bits [ 4,0 ] description reserved cache enable write enable read enable x x 0 0 dram disabled, accesses directed to pci x 0 0 1 read only, dram write protected, non- cacheable x 1 0 1 read only, dram write protected, cacheable for code accesses only x 0 1 0 write only x 0 1 1 read/write, non-cacheable x 1 1 1 read/write, cacheable note: to enable pci master access to the dram address space from c0000h to fffffh the memcs y configuration registers of the isa or eisa bridge must be properly configured. these registers must correspond to the pam registers in the pcmc. as an example, consider a bios that is implemented on the expansion bus. during the initialization process the bios can be shadowed in main memory to increase the system performance. when a bios is shadowed in main memory, it should be copied to the same address location. to shadow the bios, the attributes for that address range should be set to write only. the bios is shadowed by first doing a read of that address. this read is forwarded to the expansion bus. the cpu then does a write of the same address, which is directed to main memory. after the bios is shadowed, the attributes for that memory area are set to read only so that all writes are forwarded to the expansion bus. 52
82434LX/82434nx table 4. pam registers and associated memory segments pam reg attribute bits memory segment comments offset pam0 [ 3:0 ] r ce we re 080000h 09ffffh 512k 640k 59h pam0 [ 7:4 ] r ce we re 0f0000h 0fffffh bios area 59h pam1 [ 3:0 ] r ce we re 0c0000h 0c3fffh isa add-on bios 5ah pam1 [ 7:4 ] r ce we re 0c4000h 0c7fffh isa add-on bios 5ah pam2 [ 3:0 ] r ce we re 0c8000h 0cbfffh isa add-on bios 5bh pam2 [ 7:4 ] r ce we re 0cc000h 0cffffh isa add-on bios 5bh pam3 [ 3:0 ] r ce we re 0d0000h 0d3fffh isa add-on bios 5ch pam3 [ 7:4 ] r ce we re 0d4000h 0d7fffh isa add-on bios 5ch pam4 [ 3:0 ] r ce we re 0d8000h 0dbfffh isa add-on bios 5dh pam4 [ 7:4 ] r ce we re 0dc000h 0dffffh isa add-on bios 5dh pam5 [ 3:0 ] r ce we re 0e0000h 0e3fffh bios extension 5eh pam5 [ 7:4 ] r ce we re 0e4000h 0e7fffh bios extension 5eh pam6 [ 3:0 ] r ce we re 0e8000h 0ebfffh bios extension 5fh pam6 [ 7:4 ] r ce we re 0ec000h 0effffh bios extension 5fh dos application area (00000h-9fffh) the 640-kbyte dos application area is split into two regions. the first region is 0 512-kbyte and the second region is 512 640 kbyte. read, write, and cacheability attributes are always enabled and are not programma- ble for the 0 512 kbyte region. video buffer area (a0000h-bffffh) this 128-kbyte area is not controlled by attribute bits. cpu-initiated cycles in this region are always forwarded to pci for termination. this area is not cacheable. expansion area (c0000h-dffffh) this 128-kbyte area is divided into eight 16-kbyte segments. each segment can be assigned one of four read/write states: read-only, write-only, read/write, or disabled memory that is disabled is not remapped. cacheability status can also be specified for each segment. extended system bios area (e0000h-effffh) this 64-kbyte area is divided into four 16-kbyte segments. each segment can be assigned independent cacheability, read, and write attributes. memory segments that are disabled are not remapped elsewhere. 53
82434LX/82434nx system bios area (f0000h-fffffh) this area is a single 64-kbyte segment. this segment can be assigned cacheability, read, and write attributes. when disabled, this segment is not remapped. extended memory area (100000h-ffffffffh) the extended memory area can be split into several parts: # flash bios area from 4 gbyte to 4 gbyte 512-kbyte (aliased on isa at 16 mbytes 15.5 mbytes) # dram memory from 1 mbyte to a maximum of 192 mbytes # pci memory space from the top of dram to 4 gbyte 512-kbyte # memory space gap between the range of 1 mbyte up to 15.5 mbytes # frame buffer range mapped into pci memory space or the memory space gap. on power-up or reset the cpu vectors to the flash bios area, mapped in the range of 4 gbyte to 4 gbyte 512-kbyte. this area is physically mapped on the expansion bus. since these addresses are in the upper 4 gbyte range, the request is directed to pci. the dram memory space can occupy extended memory from a minimum of 2 mbytes up to 192 mbytes. this memory is cacheable. the address space on pci between the flash bios (4 gbyte to 4 gbyte 512 kbyte) and the top of dram (including any remapped memory) may be occupied by pci memory. this memory space is not cacheable. 3.2.20 drbedram row boundary registers address offset: 60 65h (82434LX) 60 67h (82434nx) default value: 02h attribute: read/write size: 8 bits note the address offset for each drb register is drb0 e 60h, drb1 e 61h, drb2 e 62h, drb3 e 63h, drb4 e 64h, drb5 e 65h, drb6 e 66h, and drb7 e 67h. 3.2.20.1 82434LX description the pcmc supports 6 rows of dram. each row is 64 bits wide. the dram row boundary registers define upper and lower addresses for each dram row. contents of these 8-bit registers represent the boundary addresses in mbytes. drb0 e total amount of memory in row 0 (in mbytes) drb1 e total amount of memory in row 0 a row 1 (in mbytes) drb2 e total amount of memory in row 0 a row 1 a row 2 (in mbytes) drb3 e total amount of memory in row 0 a row 1 a row 2 a row 3 (in mbytes) drb4 e total amount of memory in row 0 a row 1 a row 2 a row 3 a row 4 (in mbytes) drb5 e total amount of memory in row 0 a row 1 a row 2 a row 3 a row 4 a row 5 (in mbytes) the dram array can be configured with 256k x 36, 1m x 36 and 4m x 36 simms. each register defines an address range that will cause a particular ras y line to be asserted (e.g. if the first dram row is 2 mbytes in size then accesses within the 0 mbyte 2 mbytes range will cause ras0 y to be asserted). the dram row 54
82434LX/82434nx boundary (drb) registers are programmed with an 8-bit upper address limit value. this upper address limit is compared to a [ 27:20 ] of the host address bus, for each row, to determine if dram is being targeted. since this value is 8 bits and the resolution is 1 mbyte, the total bits compared span a 256 mbyte space. however, only 192 mbytes of main memory is supported. bits description 7:0 row boundary address in mbytes: this 8-bit value is compared against address lines a [ 27:20 ] to determine the upper address limit of a particular row, i.e. drb b previous drb e row size. row boundary address in mbytes these 8-bit values represent the upper address limits of the six rows (i.e., this row - previous row e row size). unpopulated rows have a value equal to the previous row (row size e 0). the value programmed into drb5 reflects the maximum amount of dram in the system. memory remapped at the top of dram, as a result of setting the memory space gap register, is not reflected in the drb registers. the top of memory is always determined by the value written into drb5 added to the memory space gap size (if enabled). as an example of a general purpose configuration where 3 physical rows are configured for either single-sided or double-sided simms, the memory array would be configured like the one shown in figure 8. in this configu- ration, the pcmc drives two ras y signals directly to the simm rows. if single-sided simms are populated, the even ras y signal is used and the odd ras y is not connected. if double-sided simms are used, both ras y signals are used. 290479 9 figure 8. simms and corresponding drb registers the following 2 examples describe how the drb registers are programmed for cases of single-sided and double-sided simms on a motherboard having a total of 6 simm sockets. 55
82434LX/82434nx example y 1 the memory array is populated with six single-sided 256-kbyte x 36 simms. two simms are required for each populated row making each populated row 2 mbytes in size. filling the array yields 6 mbytes total dram. the drb registers are programmed as follows: drb0 e 02h populated drb1 e 02h empty row, not double-sided simms drb2 e 04h populated drb3 e 04h empty row, not double-sided simms drb4 e 06h populated drb5 e 06h empty row, not double-sided simms, maximum memory e 6 mbytes. example y 2 as an another example, if the first four simm sockets are populated with 2 mbytes x 36 double-sided simms and the last two simm sockets are populated with 4 mbytes x 36 single-sided simms then filling the array yields 64 mbytes total dram. the drb registers are programmed as follows: drb0 e 08h populated with 8 mbytes, (/2 of the double-sided simms drb1 e 10h the other 8 mbytes of the double-sided simms drb2 e 18h populated with 8 mbytes, (/2 of the double-sided simms drb3 e 20h the other 8 mbytes of the double-sided simms drb4 e 40h populated with 32 mbytes drb5 e 40h empty row, not double-sided simms, maximum memory e 64 mbytes. 3.2.20.2 82434nx description the pcmc supports 8 rows of dram. each row is 64 bits wide. the dram row boundary registers define upper and lower addresses for each dram row. contents of these 8-bit registers are concatenated with the associated nibble of the drbe register to form 12 bit quantities that represent the row boundary addresses in mbytes. drbe [ 3:0 ] ll drb0 e total amount of memory in row 0 (in mbytes) drbe [ 7:4 ] ll drb1 e total amount of memory in row 0 a row 1 (in mbytes) drbe [ 11:8 ] ll drb2 e total amount of memory in row 0 a row 1 a row 2 (in mbytes) drbe [ 15:12 ] ll drb3 e total amount of memory in row 0 a row 1 a row 2 a row 3 (in mbytes) drbe [ 19:16 ] ll drb4 e total amount of memory in row 0 a row 1 a row 2 a row 3 a row 4 (in mbytes) drbe [ 23:20 ] ll drb5 e total amount of memory in row 0 a row 1 a row 2 a row 3 a row 4 a row 5 (in bytes) drbe [ 27:24 ] ll drb6 e total amount of memory in row 0 a row 1 a row 2 a row 3 a row 4 a row 5 a row 6 (in mbytes) drbe [ 31:28 ] ll drb7 e total amount of memory in row 0 a row 1 a row 2 a row 3 a row 4 a row 5 a row 6 a row 7 (in mbytes) the dram array can be configured with 256k x 36, 1m x 36, 4m x 36, and 16m x 36 simms. each register defines an address range that will cause a particular ras y line to be asserted (e.g. if the first dram row is 2 mbytes in size then accesses within the 0 to 2 mbytes range will cause ras0 y to be asserted). the dram row boundary (drb) registers are programmed with an 8-bit upper address limit value. the drbe register extends the programming model of this mechanism to 12 bits, however only 10 bits are implemented at this time. this upper address limit is compared to a [ 29:20 ] of the host address bus, for each row, to determine if dram is being targeted. since this value is 10 bits and the resolution is 1 mbyte, the total bits compared span a 1 gbyte space. however, other resource limits in the pcmc cap the total usable dram space at 512 mbytes. 56
82434LX/82434nx bits description 7:0 row boundary address in mbytes: this 8-bit value is concatenated with a nibble from the drbe register and then compared against address lines a [ 29:20 ] to determine the upper address limit of a particular row (i.e. drb b previous drb e row size). row boundary address in mbytes these 10-bit values represent the upper address limits of the 8 rows (i.e., this row - previous row e row size). unpopulated rows have a value equal to the previous row (row size e 0). the value programmed into drbe [ 31:28 ] ll drb7 reflects the maximum amount of dram in the system. memory remapped at the top of dram, as a result of setting the memory space gap register, is not reflected in the drb registers. the top of memory is determined by the value written into drbe [ 31:28 ] ll drb7 added to the memory space gap size (if enabled). if drbe [ 31:28 ] ll drb7 plus the memory space gap is greater than 512 mbytes then 512 mbytes of dram are available. the following 2 examples describe how the drb registers are programmed for cases of single-sided and double-sided simms on a motherboard having a total of 8 simm sockets. example y 1 the memory array is populated with eight single-sided 256-kbyte x 36 simms. two simms are required for each populated row making each populated row 2 mbytes in size. filling the array yields 8 mbytes total dram. the drb registers are programmed as follows: drbe [ 3:0 ] e 0h drb0 e 02h populated drbe [ 7:4 ] e 0h drb1 e 02h empty row, not double-sided simms drbe [ 11:8 ] e 0h drb2 e 04h populated drbe [ 15:12 ] e 0h drb3 e 04h empty row, not double-sided simms drbe [ 19:16 ] e 0h drb4 e 06h populated drbe [ 23:20 ] e 0h drb5 e 06h empty row, not double-sided simms drbe [ 27:24 ] e 0h drb6 e 08h populated drbe [ 31:28 ] e 0h drb7 e 08h empty row, not double-sided simms, max memory e 8 mbytes. example y 2 as an another example, if the first four simm sockets are populated with 2 mbyte x 36 double-sided simms and the last four simm sockets are populated with 16 mbyte x 36 single-sided simms then filling the array yields 288 mbytes total dram. the drb registers are programmed as follows: drbe [ 3:0 ] e 0h drb0 e 08h populated with 8 mbytes, (/2 of double-sided simms drbe [ 7:4 ] e 0h drb1 e 10h the other 8 mbytes of the double-sided simms drbe [ 11:8 ] e 0h drb2 e 18h populated with 8 mbytes, (/2 of double-sided simms drbe [ 15:12 ] e 0h drb3 e 20h the other 8 mbytes of the double-sided simms drbe [ 19:16 ] e 0h drb4 e a0h populated with 128 mbytes drbe [ 23:20 ] e 0h drb5 e a0h empty row, not double-sided simms drbe [ 27:24 ] e 1h drb6 e 20h populated with 128 mbytes drbe [ 31:28 ] e 1h drb7 e 20h empty row, not double-sided simms, max memory e 288 mbytes. 57
82434LX/82434nx 3.2.21 drbeedram row boundary extension register address offset: 68-6bh default value: 0000h attribute: read/write size: 32 bits the drbe register is not implemented in the 82434LX. this register contains an extension for each of the dram row boundary (drb) registers. each nibble of the drbe register is concatenated with a drb register (see drb register section for details on the use of the drb and drbe registers). 290479 10 bits description 31:0 extensions for drb0 through drb7: each nibble corresponds to a drb. the nibble of the drbe and its corresponding drb are concatenated and used to indicate the boundaries between rows of dram. 3.2.22 errcmdeerror command register address offset: 70h default value: 00h attribute: read/write size: 8 bits the error command register controls the pcmc responses to various system errors. bit 6 of the pcicmd register is the master enable for bit 3 of this register. bit 6 of the pcicmd register must be set to 1 to enable the error reporting function defined by bit 3 of this register. bits 6 and 8 of the pcicmd register are the master enables for bits 7, 6, 5, 4, and 1 of this register. both bits 6 and 8 of the pcicmd register must be set to 1 to enable the error reporting functions defined by bits 7, 6, 5, 4, and 1 of this register. 58
82434LX/82434nx bits description 7 serr y on received target abort: when this bit is set to 1 (and bit 8 of the pcicmd register is 1), the pcmc asserts serr y upon receiving a target abort. when this bit is set to 0, the pcmc is disabled from asserting serr y upon receiving a target abort. 6 serr y on transmitted pci data parity error: when this bit is set to 1 (and bits 6 and 8 of the pcicmd register are both 1), the pcmc asserts serr y when it detects a data parity error as a result of a cpu-to-pci write (perr y detected asserted). when this bit is set to 0, the pcmc is disabled from asserting serr y when data parity errors are detected via perr y . 5 82434LX: reserved 82434nx: serr y on received pci data parity error: when this bit is set to 1 (and bits 6 and 8 of the pcicmd register are both 1), the pcmc asserts serr y when it detects a data parity error as a result of a cpu-to-pci read (par incorrect with received data). in this case, the serr y signal is asserted when parity errors are detected on pci return data. when this bit is set to 0, the pcmc is disabled from asserting serr y when data parity errors are detected during a cpu-to-pci read. 4 82434LX: reserved 82434nx: serr y on pci address parity error: when this bit is set to 1 (and bits 6 and 8 of the pcicmd register are both 1), the pcmc asserts serr y when it detects an address parity error on pci transactions. when this bit is set to 0, the pcmc is disabled from asserting serr y when address parity errors are detected on pci transactions. 3 82434LX: reserved 82434nx: perr y on receiving a data parity error: this bit indicates whether the perr y signal is implemented in the system. when this bit is set to 1 (and bit 6 of the pcicmd register is 1), the pcmc asserts perr y when it detects a data parity error (par incorrect with received data), either from a cpu-to-pci read or a pci master write to memory. when this bit is set to 0 (or bit 6 of the pcicmd register is set to 0), the perr y signal is not asserted by the pcmc. 2 l2 cache parity enable: this bit indicates that the second level cache implements parity. when this bit is set to 1, bits 0 and 1 of this register control the checking of parity errors during cpu reads from the second level cache. if this bit is 0, parity is not checked when the cpu reads from the second level cache (pchk y ignored) and neither bit 1 nor bit 0 apply. 1 serr y on dram/l2 cache data parity error enable: this bit enables/disables the serr y signal for parity errors on reads from main memory or the second level cache. when this bit is set to 1 and bit 0 of this register is set to 1 (and bits 6 and 8 of the pcicmd register are set to 1), serr y is enabled upon a pchk y assertion from the cpu when reading from main memory or the second level cache. the processor indicates that a parity error was received by asserting pchk y . the pcmc then latches status information in the error status register and asserts serr y . when this bit is 0, serr y is not asserted upon detecting a parity error. bits [ 1:0 ] e 10 is a reserved combination. 0 e disable assertion of serr y upon detecting a dram/second level cache read parity error. 1 e enable assertion of serr y upon detecting a dram/second level cache read parity error. 0 mchk on dram/l2 cache data parity error enable: when this bit is set to 1, pen y is asserted for data returned from main memory or the second level cache. the processor indicates that a parity error was received by asserting the pchk y signal. in addition, the processor invokes a machine check exception, if enabled via the mce bit in cr4 in the pentium processor. the pcmc then latches status information in the error status register. when this bit is 0, pen y is not asserted. bits [ 1:0 ] e 10 is a reserved combination. 59
82434LX/82434nx 3.2.23 errstseerror status register address offset: 71h default value: 00h attribute: read/write clear size: 8 bits the error status register is an 8-bit register that reports the occurrence of pci, second level cache, and dram parity errors. this register also reports the occurrence of a cpu shutdown cycle. bits description 7 reserved 6 pci transmitted data parity error: the pcmc sets this bit t o a 1 when it detects a data parity error (perr y asserted) as a result of a cpu-to-pci write. software resets this bit to 0 by writin ga1toit. 5 82434LX: reserved 82434nx: pci received data parity error: the pcmc sets this bit t o a 1 when it detects a data parity error (par incorrect with received data) as a result of a cpu-to-pci read. software resets this bit to 0 by writin ga1toit. 4 82434LX: reserved 82434nx: pci address parity error: the pcmc sets this bit t o a 1 when it detects an address parity error (par incorrect with received address and c/be y lines) on a pci master transaction. software resets this bit to 0 by writin ga1toit. 3 main memory data parity error: the pcmc sets this bit t o a 1 when it detects a parity error from the cpu pchk y signal resulting from a cpu-to-main memory read. software resets this bit to 0 by writin ga1toit. 2 l2 cache data parity error: the pcmc sets this bit t o a 1 when it detects a parity error from the cpu pchk y signal resulting from a cpu read access that hit in the second level cache. software resets this bit to 0 by writin ga1toit. 1 reserved 0 shutdown cycle detected: the pcmc sets this bit t o a 1 when it detects a shutdown special cycle on the host bus. under this condition the pcmc drives a shutdown special cycle on pci and asserts init. software resets this bit to 0 by writin ga1toit. 60
82434LX/82434nx 3.2.24 smrsesmram space register address offset: 72h default value: 00h attribute: read/write size: 8 bits the pcmc supports a 64-kbyte smram space that can be selected to reside at the top of main memory, segment a0000 affffh or segment b0000 bffffh. the smm space defined by this register is not cache- able. this register defines a mechanism that allows the cpu to execute code out of the smm space at either a0000h or b0000h while accessing the frame buffer on pci. the smram enable bit in the dram control register must be 1 to enable the features defined by this register. register bits [ 5:3 ] apply only when segment a0000-affffh or b0000-bffffh are selected. bits description 7:6 reserved 5 open smram space (oss): when oss e 1, the cpu can access smm space without being in smm mode. that is, accesses to smm space are permitted even with smiact y negated. this bit is intended to be used during post to allow the cpu to initialize smram space before the first smi y interrupt is issued. 4 close smram space (css): when css e 1 and smram is enabled, cpu code accesses to the smm memory range are directed to smm space in main memory and data accesses are forwarded to pci. this bit allows the cpu to read and write the frame buffer on pci while executing smm code. when css e 0 and smram is enabled, all accesses to the smram memory range, both code and data, are directed to smram (main memory). 3 lock smram space (lss): when lss e 1, this bit prevents the smm space from being manually opened, effectively disabling bit 5 of this register. only a power-on reset can set this bit to 0. 2:0 smm base segment (sbs): this field defines the 64 kbyte base segment where smm space is located. the memory that is defined by this field is non-cacheable. bits [ 2:0 ] smram location bits [ 2:0 ] smram location 000 top of main memory 100 reserved 001 reserved 101 reserved 010 a0000 affffh 110 reserved 011 b0000 bffffh 111 reserved 3.2.25 msgememory space gap register address offset: 78-79h default value: 00h attribute: read/write size: 16 bits the memory space gap register defines the starting address and size of a gap in main memory. this register accommodates isa devices that have their memory mapped into the 1 mbyte 15.5 mbyte range (e.g., an isa lan card or an isa frame buffer). the memory space gap register defines a hole in main memory that transfers the cycles in this address space to the pci bus instead of main memory. this area is not cacheable. the memory space gap starting address must be a multiple of the memory space gap size. for example, a 2 mbyte gap must start at 2, 4, 6, 8, 10, 12, or 14 mbytes. 61
82434LX/82434nx note: memory that is disabled by the gap created by this register is remapped to the top of memory. this remapped memory is accessible, except in the case where this would cause the top of main memory to exceed 192 mbytes (or 512 mbytes for the 82434nx). bits description 15 memory space gap enable (msge): msge enables and disables the memory space gap. when msge is set to 1, the cpu accesses to the address range defined by this register are forwarded to pci bus. the size of the gap created in main memory causes a corresponding amount of dram to be remapped at the top of main memory (top specified by drb registers). if the frame buffer range is programmed below 16 mbytes and within main memory space, the msg register must include the frame buffer range. when msge is reset to 0, the memory space gap is disabled. 14:12 memory space gap size (msgs): this 3 bit field defines the size of the memory space gap. if the frame buffer range is programmed below 16 mbytes and within main memory space, this register must include the frame buffer range. the amount of main memory specified by these bits is remapped to the top of main memory. bit [ 14:12 ] memory gap size 000 1 mbyte 001 2 mbytes 011 4 mbytes 111 8 mbytes note: all other combinations are reserved. 11:8 reserved 7:4 memory space gap starting address (msgsa): these 4 bits define the starting address of the memory space gap in the space from 1 mbyte 16 mbytes. these bits are compared against a [ 23:20 ] . the memory space gap starting address must be a multiple of the memory space gap size. for example , a 2 mbytes gap must start at 2, 4, 6, 8, 10, 12, or 14 mbytes. 3:0 reserved 3.2.26 fbreframe buffer range register address offset: 7c-7fh default value: 0000h attribute: read/write size: 32 bits this 32-bit register enables and disables a frame buffer area and provides attribute settings for the frame buffer area. the attributes defined in this register are intended to increase the performance of the frame buffer. the fbr register can be used to accommodate pci devices that have their memory mapped onto pci from the top of main memory to 4 gbyte 512-kbyte range (e.g., a linear frame buffer). if the frame buffer range is located within the 1 mbyte 16 mbytes main memory region where dram is populated, the memory space gap register must be programmed to include the frame buffer range. 62
82434LX/82434nx bits description 31:20 buffer offset (bo): bo defines the starting address of the frame buffer address space in increments of 1 mbyte. this 12-bit field is compared directly against a [ 31:20 ] . the frame buffer range can either be located at the top of memory, including remapped memory or within the memory space gap (i.e., frame buffer range programmed below 16 mbytes and within main memory space. when bits [ 31:20 ] e 0000h and bit 12 e 0, all features defined by this register are disabled. 19:14 reserved 13 byte merging (bm): byte merging permits cpu-to-pci byte writes to the lbx posted write buffer to be combined into a single transfer on the pci bus, when appropriate. when bm is set to 1, byte merging on cpu-to-pci posted write cycles is enabled. when bm is reset to 0, byte merging is disabled. 12 128k vga range attribute enable (vrae): when vrae e 1, the attributes defined in this register (bits [ 13, 10:7 ] ) also apply to the vga memory range of a0000h bffffh regardless of the value programmed in the buffer offset field. when vrae e 0, the attributes do not apply to the vga memory range. note that this bit only affects the mentioned attributes of the vga memory range and does not enable or disable accesses to the vga memory range. 11:10 reserved 9 no lock requests (nlr): when nlr is set to 1, the pcmc never requests exclusive access to a pci resource via the pci lock y signal in the range defined by this register. when nlr is reset to 0, exclusive access via the pci lock y signal in the range defined by this register is enabled. 8 reserved 7 transparent buffer writes (tbw): when set to a 1, this bit indicates that writes to the frame buffer range need not be flushed for deadlock or coherence reasons on synchronization events (i.e., pci master reads, and the flshbuf y /memreq y protocol). when reset to 0, this bit indicates that upon synchronization events, flushing is required for frame buffer writes posted in the cpu-to-pci write buffer in the lbx 6:4 reserved 3:0 buffer range (br): these bits define the size of the frame buffer address space, allowing up to 16 mbytes of frame buffer. if the frame buffer range is within the memory space gap, the buffer range is limited to 8 mbytes and must be included within the memory space gap. the bits listed below in the reserved buffer offset (bo) bits column are ignored by the pcmc for the corresponding buffer sizes. bits [ 3:0 ] buffer size reserved buffer offset (bo) bits 0000 1 mbyte none 0001 2 mbytes [ 20 ] 0011 4 mbytes [ 21:20 ] 0111 8 mbytes [ 22:20 ] 1111 16 mbytes [ 23:20 ] note: (all other combinations are reserved) 63
82434LX/82434nx 4.0 pcmc address map the pentium processor has two distinct physical ad- dress spaces: memory and i/o. the memory ad- dress space is 4 gbytes and the i/o address space is 64 kbytes. the pcmc maps accesses to these address spaces as described in this section. 4.1 cpu memory address map figure 9 shows the address map for the 4 gbyte host cpu memory address space. depending on the address range and whether a memory gap is enabled via the msg register, the pcmc forwards cpu memory accesses to either main memory or pci memory. accesses forwarded to main memory invoke operations on the dram interface and ac- cesses forwarded to pci memory invoke operations on pci. mapping to the pci bus permits pci or eisa/isa bus-based memory. the main memory size ranges from 2 mbytes 192 mbytes for the 82434LX and 2 mbytes 512 mbytes for the 82434nx. memory accesses above 192 mbytes (512 mbytes for the 82434nx) are always forwarded to pci. in addition, a memory gap can be created in the 1 mbyte 16 mbytes region that provides a window to pci-based memo- ry. the location and size of the gap is programma- ble. accesses to addresses in the gap are ignored by the dram controller and forwarded to pci. note that cpu memory accesses that are forwarded to pci (including the memory space gap) are not cacheable. only main memory controlled by the pcmc dram interface is cacheable. 4.2 system management rame smram the pcmc supports the use of main memory as system management ram (smram) enabling the use of system management mode. this function is enabled and disabled via the dram control regis- ter. when this function is disabled, the pcmc mem- ory map is defined by the drb and pam registers. when smram is enabled, the pcmc reserves the top 64-kbytes of main memory for use as smram. smram can also be placed at a0000 affffh or b0000 bffffh via the smram space register. enhanced smram features can also be enabled via this register. pci masters can not access smram when it is programmed to the a or b segments. 290479 11 figure 9. cpu memory address mapefull range 64
82434LX/82434nx however, pci masters can access smram when the top of memory is selected. when the 82434nx pcmc detects a cpu stop grant special cycle (m/io y e 0, d/c y e 0, w/r y e 1, a4 e 1, be [ 7:0 ] y e fbh), it generates a pci stop grant special cycle, with 0002h in the message field (ad [ 15:0 ] ) and 0012h in the message dependent data field (ad [ 31:16 ] ) during the first data phase (irdy y asserted). 4.3 pc compatibility range the pc compatibility range is the first mbyte of the memory map. the 512 kbyte 1 mbyte range is sub- divided into several regions as shown in figure 10. each region is provided with programmable attri- butes in the pam registers. the attributes are read enable (re), write enable (we) and cache enable (ce). the attributes determine readability, writeabili- ty and cacheability of the corresponding memory re- gion. when the associated bit in the pam register is set to a 1, the attribute is enabled and when set to a 0 the attribute is disabled. the following rules apply for cacheability in the first level and second level caches: 1. if re e 1, we e 1, and ce e 1, the region is cacheable in the first level and second level caches. 2. if re e 1, we e 0, and ce e 1, the region is cacheable only on code reads (i.e., d/c y e 0). data reads do not result in a line fill. writes to the region are not serviced by the secondary cache, but are forwarded to pci. 290479 12 figure 10. cpu memory address mapepc compatibility range 65
82434LX/82434nx the re and we bits for each region are used to shadow bios rom in main memory for improved system performance. to shadow a bios area, re is reset to 0 and we is set to 1. re is set to 1 and we is reset to 0. any writes to the bios area are for- warded to pci. 4.4 i/o address map i/o devices (other than the pcmc) are not support- ed on the host bus. the pcmc generates pci bus cycles for all cpu i/o accesses, except to the pcmc internal registers. figure 11 shows the map- ping for the cpu i/o address space. for the 82434LX, three pcmc registers are located in the cpu i/o address spaceethe configuration space enable (cse) register, the turbo-reset control (trc) register, and the forward (forw) register. 290479 13 notes: 1. this 82434nx register is only visible when configuration access mechanism y 1 is enabled (via bit 31 of the con- fadd register). otherwise, this i/o range is in pci i/o space. 2. this 82434nx register is accessed during dword read/writes to 0cf8h. byte or word cycles access the correspond- ing 8-bit registers, even if configuration access mechanism y 1 is enabled. figure 11. cpu i/o address map 66
82434LX/82434nx for the 82434nx, six pcmc registers are located in the cpu i/o address spaceethe configuration space enable (cse) register, the configuration ad- dress register (confadd), the turbo-reset con- trol (trc) register, the forward (forw) register, the pci mechanism control (pmc) register, and the configuration data (confdata) register. except for the i/o locations of the above mentioned registers, all other cpu i/o accesses are mapped to either pci i/o space or pci configuration space. if the access is to pci i/o space, the pci address is the same as the cpu address. if the access is to pci configuration space, the cpu address is mapped to a configuration space address as described in sec- tion 3.0, register description. if configuration space is enabled via the cse regis- ter (access mechanism y 2), the pcmc maps ac- cesses in the address range of c100h to cfffh to pci configuration space. accesses to the pcmc configuration register range (c000h to c0ffh) are intercepted by the pcmc and not forwarded to pci. if the configuration space is disabled in the cse register, cpu accesses to the configuration ad- dress range (c000h to cfffh) are forwarded to pci i/o space. 5.0 second level cache interface this section describes the second level cache inter- face for the 82434LX cache (section 5.1) and the 82434nx cache (section 5.2). the differences are in the following areas: 1. the 82434LX supports both write-through and write-back cache policies. the 82434nx only supports the write-back policy. 2. the 82434LX timings are for 60 and 66 mhz and the 82434nx timings are for 50, 60, and 66 mhz. note that the cycle latencies for 60 and 66 mhz are the same for both devices. 3. when burst srams are used to implement the secondary cache, address latches are not need- ed for the 82434nx type sram connectivity. however, a control bit has been added to the 82434nx that permits address latches for 82434LX type sram connectivity. 4. a low-power second level cache standby mode has been added to the 82434nx. 5. there are new or changed cache control bits as indicated by the shading in section 3.0, register description. for example, the 82434nx supports zero wait-state cache at 50 mhz via the zero wait-state control bit. note: # second level cache sizes and organization are the same for the 82434LX and 82434nx. # the general operation of the second level cache write-back policy is the same for the 82434LX and 82434nx. for example, the valid and modified bits operate the same for both devices. in addition, snoop opera- tions are the same for both devices, as well as the handling of flush, flush ac- knowledge, and write-back special cycles. 5.1 82434LX cache the 82434LX pcmc integrates a high performance write-back/write-through second level cache con- troller providing integrated tags and a full first level and second level cache coherency mechanism. the second level cache controller can be configured to support either a 256-kbyte cache or a 512 kbyte cache using either synchronous burst srams or standard asynchronous srams. the cache is direct mapped and can be configured to support either a write-back or write-through write policy. parity on the second level cache data srams is optional. the 82434LX contains 4096 address tags. each tag represents a sector in the second level cache. if the second level cache is 256-kbyte, each tag repre- sents two cache lines. if the second level cache is 512-kbyte, each tag represents four cache lines. thus, in the 256-kbyte configuration each sector contains two lines. in the 512-kbyte configuration, each sector contains four lines. valid and modified status bits are kept on a per line basis. thus, in the case of a 256-kbyte cache each tag has two valid bits and two modified bits associated with it. in the case of a 512-kbyte cache each tag has four valid and four modified bits associated with it. upon a cpu read cache miss, the pcmc inspects the valid and modified bits within the addressed sector and writes back to main memory only the lines marked both valid and modified. all of the lines in the sector are then invalidated. the line fill will then occur and the valid bit associated with the allocated line will be set. only the requested line will be fetched from main memory and written into the cache. if no write- back is required, all of the lines in the sector are marked invalid. the line fill then occurs and the valid bit associated with the allocated line will be set. lines are not allocated on write misses. when a cpu write hits a line in the second level cache, the modified bit for the line is set. 67
82434LX/82434nx the second level cache is optional to allow the 82434LX pcmc to be used in a low cost configura- tion. a 256-kbyte cache is implemented with a sin- gle bank of eight 32 k x 9 srams if parity is support- ed or 32k x 8 srams if parity is not supported on the cache. a 512-kbyte cache is implemented with four 64k x 18 srams if parity is supported or 64k x 16 srams if parity is not supported on the cache. two 74as373 latches complete the cache. only main memory controlled by the pcmc dram inter- face is cached. memory on pci is not cached. figure 12 and figure 13 depict the organization of the internal tags in the pcmc configured for a 256 kbyte cache and a 512-kbyte cache. 290479 14 figure 12. pcmc internal tags with 256-kbyte cache 68
82434LX/82434nx 290479 15 figure 13. pcmc internal tags with 512-kbyte cache in the 256-kbyte cache configuration a [ 17:6 ] form the tag ram index. the ten tag bits read from the tag ram are compared against a [ 27:18 ] from the host address bus. two valid bits and two modified bits are kept per tag in this configuration. host ad- dress bit 5 is used to select between lines 0 and 1 within a sector. in the 512-kbyte cache configura- tion a [ 18:7 ] form the tag ram index. the nine bits read from the tag ram are compared against a [ 27:19 ] from the host bus. four valid bits and four modified bits are kept per tag. host address bits 5 and 6 are used to select between lines 0, 1, 2 and 3 within a sector. the secondary cache controller register at offset 52h in configuration space controls the secondary cache size, write and allocation policies, and sram type. the cache can also be enabled and disabled via this register. figure 14 through figure 18 show the connections between the pcmc and the external cache data srams and latches. 69
82434LX/82434nx 290479 16 figure 14. 82434LX connections to 256-kbyte cache with standard sram 70
82434LX/82434nx 290479 17 figure 15. 82434LX connections to 512-kbyte cache with standard sram 71
82434LX/82434nx 290479 18 figure 16. 82434LX connections to 512-kbyte cache with dual-byte select standard srams 72
82434LX/82434nx 290479 19 figure 17. 82434LX connections to 256-kbyte cache with burst sram 73
82434LX/82434nx 290479 20 figure 18. 82434LX connections for 512-kbyte cache with burst sram 74
82434LX/82434nx when cale is asserted, ha [ 18:7 ] flow through the address latch. when cale is negated the address is captured in the latch allowing the processor to pipe- line the next bus cycle onto the address bus. two copies of ca [ 6:3 ] , coe y , cads y and cadv y are provided to reduce capacitive loading. both copies should be used when the second level cache is im- plemented with eight 32k x 8 or 32k x 9 srams. either both copies or only one copy can be used with 64k x 18 or 64k x 16 srams as determined by the system board layout and timing analysis. the two copies are always driven to the same logic level. caa [ 4:3 ] and cab [ 4:3 ] are used to count through the pentium processor burst order when standard srams are used to implement the cache. with burst srams, the address counting is provided inside the srams. in this case, caa [ 4:3 ] and cab [ 4:3 ] are only used at the beginning of a cycle to load the initial low order address bits into the burst srams. during cpu accesses, host address lines 6 and 5 are propagated to the caa [ 6:5 ] and cab [ 6:5 ] lines and are internally latched. when a cpu read cycle forces a line replacement in the sec- ond level cache, all modified lines within the ad- dressed sector are written back to main memory. the pcmc uses caa [ 6:5 ] and cab [ 6:5 ] to select among the lines within the sector. the cache output enables (coe [ 1:0 ] y ) are asserted to enable the srams to drive data onto the host data bus. the cache write enables (cwe [ 7:0 ] y ) allow byte con- trol during cpu writes to the second level cache. an asynchronous sram 512-kbyte cache can be implemented with two different types of sram byte control. figure 15 depicts the pcmc connections to a 512 kbyte cache using 64k x 18 srams or 64k x 16 srams with two write enables per sram. each sram has a high and low write enable. figure 16 depicts the pcmc connections to a 512-kbyte cache using 64k x 18 srams or 64k x 16 srams with two byte select lines per sram. each sram has a high and low byte select. the type of cache byte control (write enable or byte select) is programmed in the cache byte control bit in the secondary cache control register at configu- ration space offset 52h. when this bit is set to 0, byte select control is used. in this mode, the cbs [ 7:0 ] y lines are multiplexed onto pins 90, 91, and 95-100 and cr/w [ 1:0 ] y pins are multiplexed onto pins 93 and 94. when this bit is set to 1, byte write enable control is used. in this mode, the cwe [ 7:0 ] y lines are multiplexed onto pins 90, 91, and 95-100. cads [ 1:0 ] y and cadv [ 1:0 ] y are only used with burst srams. the cache address strobes (cads [ 1:0 ] y ) are asserted to cause the burst srams to latch the cache address at the be- ginning of a second level cache access. cads [ 1:0 ] y can be connected to either adsp y or adsc y on the srams. the cache advance signals (cadv [ 1:0 ] y ) are asserted to cause the burst srams to advance to the next address of the burst sequence. 5.1.1 clock latencies (82434LX) table 5 and table 6 list the latencies for various cpu transfers to or from the second level cache for standard srams and burst srams. standard sram access times of 12 ns and 15 ns are recom- mended for 66 mhz and 60 mhz operation, respec- tively. burst sram clock access times of 8 ns and 9 ns are recommended for 66 mhz and 60 mhz op- eration, respectively. precise sram timing require- ments should be determined by system board elec- trical simulation with sram i/o buffer models. table 5. second level cache latencies with standard sram (82434LX) cycle type hclk count burst read 3-2-2-2 burst write 4-2-2-2 single read 3 single write 4 pipelined back to back burst reads 3-2-2-2/3-2-2-2 burst read followed by pipelined write 3-2-2-2/4 75
82434LX/82434nx table 6. second level cache latencies with burst sram (82434LX) cycle type hclk count burst read 3-1-1-1 burst write 3-1-1-1 single read 3 single write 3 pipelined back to back burst reads 3-1-1-1/1-1-1-1 read followed by pipelined write 3-1-1-1/2 5.1.2 standard sram cache cycles (82434LX) the following sections describe the activity of the second level cache interface when standard asyn- chronous srams are used to implement the cache. 5.1.2.1 burst read (82434LX) figure 19 depicts a burst read from the second level cache with standard srams. the cpu initiates the read cycle by driving address and status onto the bus and asserting ads y . initially, the ca [ 6:3 ] are a propagation delay from the host address lines a [ 6:3 ] . upon sampling w/r y active and m/io y in- active, while ads y is asserted, the pcmc asserts coe y to begin a read cycle from the srams. cale is negated, latching the address lines on the sram address inputs, allowing the cpu to pipeline a new address onto the bus. ca [ 4:3 ] cycle through the pentium processor burst order, completing the cy- cle. pen y is asserted with the first brdy y and negated with the last brdy y if parity is implement- ed on the second level cache data srams and the mchk dram/second level cache data parity bit in the error command register (offset 70h) is set. figure 20 depicts a burst read from the second level cache with standard 16- or 18-bit wide dual-byte se- lect srams. a single read cycle from the second level cache is very similar to the first transfer of a burst read cycle. cale is not negated throughout the cycle. coe y is asserted as shown above, but is negated with brdy y . when the secondary cache allocation (sca) bit in the secondary cache control register is set to 1, the pcmc performs a line fill in the secondary cache, even if the cache y signal from the cpu is inactive. in this case, ahold is asserted to prevent the cpu from beginning a new cycle while the sec- ond level cache line fill is completing. back-to-back pipelined burst reads from the second level cache are shown in the figure 21. 76
82434LX/82434nx 290479 21 figure 19. cpu burst read from second level cache with standard sram (82434LX) 290479 22 figure 20. burst read from second level cache with dual-byte select srams (82434LX) 77
82434LX/82434nx 290479 23 figure 21. pipelined back-to-back burst reads from second level cache with standard sram (82434LX) due to assertion of na y , the cpu drives a new ad- dress onto the bus before the first cycle is complete. in this case, the second cycle is a hit in the second level cache. immediately upon completion of the first read cycle, the pcmc begins the second cycle. when the first cycle completes, the pcmc drives the new address to the srams on ca [ 6:3 ] and asserts cale. the second cycle is very similar to the first, completing at a rate of 3-2-2-2. the cache address lines must be held at the sram address inputs until the first cycle completes. only after the last brdy y is returned, can cale be asserted and ca [ 6:3 ] be changed. thus, the pipelined cycle completes at the same rate as a non-pipelined cycle. 5.1.2.2 burst write (82434LX) a burst write cycle is used to write back a cache line from the first level cache to either the second level cache or dram. figure 22 depicts a burst write cy- cle to the second level cache with standard srams. the cpu initiates the write cycle by driving address and status onto the bus and asserting ads y . initial- ly, the ca [ 6:3 ] propagate from the host address lines a [ 6:3 ] . cale is negated, latching the address lines on the sram address inputs, allowing the cpu to pipeline a new address onto the bus. burst write cycles from the pentium processor always begin with the low order qword and advances to the high order qword. cwe [ 7:0 ] y are generated from an in- ternally delayed version of hclk, providing address setup time to cwe [ 7:0 ] y falling and data setup time to cwe [ 7:0 ] y rising edges. hig [ 4:0 ] are driven to pcmwq (post cpu to memory write buffer qword) only when the pcmc is programmed for a write- through write policy. when programmed for write- back mode, the modified bit associated with the line is set within the pcmc. the single write cycle is very similar to the first write of a burst write cycle. a burst read cycle followed by a pipelined write cycle with standard srams is depicted in figure 24. 78
82434LX/82434nx 290479 24 figure 22. burst write to second level cache with standard sram (82434LX) 290479 25 figure 23. burst write to second level cache with dual-byte select standard srams (82434LX) 79
82434LX/82434nx 290479 26 figure 24. burst read followed by pipelined write with standard sram (82434LX) 5.1.2.3 cache line fill (82434LX) if the cpu issues a memory read cycle to cacheable memory that is not in the second level cache, a first and second level cache line fill occurs. figure 25 depicts a cpu read cycle that results in a line fill into the first and second level caches. figure 27 depicts the host bus activity during a cpu read cycle that forces a write-back from the second level cache to the cpu-to-memory posted write buff- er as the dram read cycle begins. 80
82434LX/82434nx 290479 27 figure 25. cache line fill with standard sram, dram page hit (82434LX) 81
82434LX/82434nx 290479 28 figure 26. cache line fill with dual-byte select standard sram, dram page hit (82434LX) 82
82434LX/82434nx 290479 29 figure 27. cpu cache read miss, write-back, line fill with standard sram (82434LX) the cpu issues a memory read cycle that misses in the second level cache. in this instance, a modified line in the second level cache must be written back to main memory before the new line can be filled into the cache. the pcmc inspects the valid and modified bits for each of the lines within the ad- dressed sector and writes back only the valid lines within the sector that are in the modified state. dur- ing the write-back cycle, ca [ 4:3 ] begin with the ini- tial value driven by the pentium processor and pro- ceed in the pentium processor burst order. ca [ 6:5 ] are used to count through the lines within the ad- dressed sector. when two or more lines must be written back to main memory, ca [ 6:5 ] count in the direction from line 0 to line 3. ca [ 6:5 ] advance to the next line to be written back to main memory, skipping lines that are not modified. figure 23 de- picts the case of just one of the lines in a sector being written back to main memory. in this case, the entire line can be posted in the cpu-to-main memo- ry posted write buffer by driving the hig [ 4:0 ] lines to the pcmwq command as each qword is read from the cache. at the same time, the required dram read cycle is beginning. as soon as the de-allocated line is written into the posted write buffer, the hig [ 4:0 ] lines are driven to cmr (cpu memory read) to allow data to propagate from the dram data lines to the cpu data lines. the cwe [ 7:0 ] y lines are not generated from a delayed version of hclk (as they are in the case of cpu to second level cache burst write), but from ordinary hclk ris- ing edges. cmr is driven on the hig [ 4:0 ] lines 83
82434LX/82434nx throughout the dram read portion of the cycle. with the fourth assertion of brdy y the hig [ 4:0 ] lines change to nopc. the lbxs however, do not tri- state the host data lines until mdle rises. cwe [ 7:0 ] y and mdle track such that mdle will not rise before cwe [ 7:0 ] y . thus, the lbxs contin- ue to drive the host data lines until cwe [ 7:0 ] y are negated. ca [ 6:3 ] remain at the valid values until the clock after the last brdy y , providing address hold time to cwe [ 7:0 ] y rising. pen y is asserted as shown if the mchk dram/l2 cache data parity error bit in the error command register (offset 70h) is set. if the second level cache supports parity, pen y is always asserted during cpu read cycles in the third clock in case the cycle hits in the cache. if more than one line must be written back to main memory, the pcmc fills the cpu-to-main memory posted write buffer and loads another qword into the buffer as each qword write completes into main memory. the writes into dram proceed as page hit write cycles from one line to the next, completing at a rate of x-4-4-4-5-4-4-4-5-4-4-4 for a three line write-back. all modified lines except for the last one to be written back are posted and written to memory before the dram read cycle begins. the last line to be written back is posted as the dram read cycle begins. thus, the read data is returned to the cpu before the last line is retired to memory. the line which was written into the second level cache is marked valid and unmodified by the pcmc. all the other lines in the sector are marked invalid. a subsequent cpu read cycle which hits in the same sector (but a different line) in the second level cache would then simply result in a line fill without any write-back. 5.1.3 burst sram cache cycles (82434LX) the following sections show the activity of the sec- ond level cache interface when burst srams are used for the second level cache. 5.1.3.1 burst read (82434LX) figure 28 depicts a burst read from the second level cache with burst srams. 290479 30 figure 28. cpu burst read from second level cache with burst sram (82434LX) 84
82434LX/82434nx the cycle begins with the cpu driving address and status onto host bus and asserting ads y . the pcmc asserts cads y and coe y in the second clock. after the address is latched by the burst srams and the pcmc determines that no write- back cycles are required from the second level cache, cale is negated. back-to-back burst reads from the second level cache are shown in figure 29. when the secondary cache allocation (sca) bit in the secondary cache control register is set to 1, the pcmc performs a line fill in the secondary cache, even if the cache y signal from the cpu is negated. in this case, ahold is asserted to prevent the cpu from beginning a new cycle while the sec- ond level cache line fill is completing. back-to-back burst reads which hit in the second level cache complete at a rate of 3-1-1-1/1-1-1-1 with burst srams. as the last brdy y is being re- turned to the cpu, the pcmc asserts cads y caus- ing the srams to latch the new address. this allows the data for the second cycle to be transferred to the cpu on the clock after the first cycle completes. 290479 31 figure 29. pipelined back-to-back burst reads from second level cache (82434LX) 85
82434LX/82434nx 5.1.3.2 burst write (82434LX) a burst write cycle is used to write back a line from the first level cache to either the second level cache or dram. a burst write cycle from the first level cache to the second level cache is shown in fig- ure 30. the pentium processor always writes back lines starting with the low order qword advancing to the high order qword. cads y is asserted in the second clock. cwe [ 7:0 ] y and brdy y are asserted in the third clock. cadv y assertion is delayed by one clock relative to the burst read cycle. hig [ 4:0 ] are driven to pcmwq (post cpu-to-memory write buff- er qword) only when the pcmc is programmed for a write-through write policy. when programmed for write-back mode, the modified bit associated with the line is set within the pcmc. the single write is very similar to the first write in a burst write. cads y is asserted in the second clock. brdy y and cwe [ 7:0 ] y are asserted in the third clock. a burst read cycle followed by a pipelined single write cycle is depicted in figure 31. 290479 32 figure 30. burst write to second level cache with burst sram (82434LX) 86
82434LX/82434nx 290479 33 figure 31. burst read followed by pipelined single write cycle with burst sram (82434LX) 87
82434LX/82434nx 5.1.3.3 cache line fill (82434LX) if the cpu issues a memory read cycle to cacheable memory which does not hit in the second level cache, a cache line fill occurs. figure 32 depicts a first and second level cache line fill with burst srams. figure 33 depicts a cpu read cycle which forces a write-back in the second level cache. 290479 34 figure 32. cache line fill with burst sram, dram page hit, 7-4-4-4 timing (82434LX) 88
82434LX/82434nx 290479 35 figure 33. cpu cache read miss, write-back, line fill with burst sram (82434LX) the cpu issues a memory read cycle which misses in the second level cache. in this instance, a modi- fied line in the second level cache must be written back to main memory before the new line can be filled into the cache. the pcmc inspects the valid and modified bits for each of the lines within the addressed sector and writes back only the valid lines within the sector that are marked modified. ca [ 6:5 ] are used to count through the lines within the addressed sector. when two or more lines must be written back to main memory, ca [ 6:5 ] count in the direction from line 0 to line 3 after each line is written back. figure 29 depicts the case of just one 89
82434LX/82434nx of the lines in a sector being written back to main memory. in this case, the entire line can be posted in the cpu-to-memory posted write buffer by driving the hig [ 4:0 ] lines to pcmwq as each qword is read from the cache. at the same time, the required dram read cycle is beginning. after the de-allocat- ed line is written into the posted write buffer, the hig [ 4:0 ] lines are driven to cmr (cpu memory read) to allow data to propagate from the dram data lines to the cpu data lines. figure 29 assumes that the read from dram is a page hit and thus the first qword is already read from the drams when the transfer from cache to the cpu to memory post- ing buffer is complete. the rest of the dram cycle completes at a -4-4-4 rate. cadv y is asserted with the last three brdy y assertions. cmr is driven on the hig [ 4:0 ] lines throughout the dram read por- tion of the cycle. upon the fourth assertion of brdy y the hig [ 4:0 ] lines change to nopc. pen y is asserted as shown if the mchk dram/l2 cache data parity error bit in the error command register (offset 70h) is set. if the second level cache supports parity, pen y is always asserted during cpu read cycles in clock 3 in case the cycle hits in the cache. if more than one line must be written back to main memory, the pcmc fills the cpu-to-main memory posted write buffer and loads another qword into the buffer as each qword write completes into main memory. the writes into dram proceed as page hit write cycles from one line to the next, completing at a rate of x-4-4-4-5-4-4-4-5-4-4-4 for a three line write-back when programmed for x-4-4-4 dram write timing or x-3-3-3-4-3-3-3-4-3-3-3 when pro- grammed for x-3-3-3 dram write timing. all modi- fied lines except for the last one to be written back to memory are posted and retired to memory before the dram read cycle begins. the last line to be writ- ten back is posted as the dram read cycle begins. thus, the read data is returned to the cpu before the last line is retired to memory. the line which was written into the second level cache is marked valid and unmodified by the pcmc. all the other lines in the block are marked invalid. a subsequent cpu read cycle which hits the same sector (but a different line) in the second level cache results in a line fill without any write-back. 5.1.4 snoop cycles snoop cycles are the same for the 82434LX and 82434nx. the inquire cycle is used to probe the first level and second level caches when a pci master attempts to access main memory. this is done to maintain coherency between the first and second level caches and main memory. when a pci master first attempts to access main memory a snoop re- quest is generated inside the pcmc. the pcmc supports up to two outstanding cycles on the cpu address bus at a time. outstanding cycles include both cpu initiated cycles and snoop cycles. thus, if the pentium processor pipelines a second cycle onto the host address bus, the pcmc will not issue a snoop cycle until the first cpu cycle terminates. if the pcmc were to initiate a snoop cycle before the first cpu cycle were complete then for a brief period of time, three cycles would be outstanding. thus, a snoop request is serviced with a snoop cycle only when either no cycle is outstanding on the cpu bus or one cycle is outstanding. snoop cycles are performed by driving the pci mas- ter address onto the cpu address bus and asserting eads y . the pentium processor then performs a tag lookup to determine if the addressed memory is in the first level cache. at the same time the pcmc performs an internal tag lookup to determine if the addressed memory is in the second level cache. ta- ble 7 describes how a pci master read from main memory is serviced by the pcmc. 90
82434LX/82434nx table 7. data transfers for pci master reads from main memory snoop result action first level second level cache cache miss miss data is transferred from dram to pci. miss hit unmodified line data is transferred directly from second level cache to pci. the line remains valid and unmodified in the second level cache. miss hit modified line data is transferred directly from second level cache to pci. line remains valid and modified in the second level cache. the line is not written to dram. hit unmodified line miss data is transferred from dram to pci. hit unmodified line hit unmodified line data is transferred directly from second level cache to pci. the line remains valid and unmodified in the second level cache. hit unmodified line hit modified line data is transferred directly from second level cache to pci. line remains valid and modified in the second level cache. the line is not written to dram. hit modified line miss a write-back from first level cache occurs. the data is sent to both pci and the cpu-to-memory posted write buffer. the cpu-to-memory posted write buffer is then written to memory. hit modified line hit unmodified line a write-back from first level cache occurs. the data is posted to pci and written into the second level cache. when the second level cache is in write-back mode, the line is marked modified and is not written to dram. when the second level cache is in write-through mode, the line is posted and then written to dram. hit modified line hit modified line a write-back from first level cache occurs. the data is posted to pci and written into the second level cache. the line is not written to dram. this scenario can only occur when the second level cache is in write-back mode. pci master write cycles never result in a write direct- ly into the second level cache. a snoop hit to a modi- fied line in either the first level or second level cache results in a write-back of the line to main memory. the line is invalidated and the pci write to main memory occurs after the write-back completes. the other lines in the sector are not written back to main memory or invalidated. a pci master write snoop hit to an unmodified line in either the first level or sec- ond level cache results in the line being invalidated. table 8 describes the actions taken by the pcmc when a pci master writes to main memory. 91
82434LX/82434nx table 8. data transfers for pci master writes to main memory snoop result action first level second level cache cache miss miss the pci master write data is transferred from pci to dram. miss hit unmodified line the pci master write data is transferred from pci to dram. the line is invalidated in the second level cache. miss hit modified line a write-back from second level cache to dram occurs. the pci master write data is then written to dram. the line is invalidated in the second level cache. hit unmodified line miss the first level cache line is invalidated. the pci master write data is written to dram. hit unmodified line hit unmodified line the line is invalidated in both the first level and second level caches. the pci master write data is written to dram. hit unmodified line hit modified line the first level cache line is invalidated. the second level cache line is written back to main memory and invalidated. the pci master write data is then written to dram. hit modified line miss the first level cache line is written back to dram and invalidated. the pci master write data is then written to dram. hit modified line hit unmodified line the first level cache line is written back to dram and invalidated. the second level cache line is invalidated. the pci master write data is then written to dram. hit modified line hit modified line the first level cache line is written back to dram and invalidated. the second level cache line is invalidated. the pci master write data is then written to dram. a snoop hit results in one of three transfers; a write- back from the first level cache posted to the lbxs, a write-back from the second level cache posted to the lbxs or a write-back from the first level cache posted to the lbxs and written to the second level cache. a snoop cycle that does not result in a write- back is depicted in figure 34. 92
82434LX/82434nx 290479 36 figure 34. snoop hit to unmodified line in first level cache or snoop miss the pcmc begins to service the snoop request by asserting ahold, causing the pentium processor to tri-state the address bus in the clock after assertion. in the case of a pci master read cycle, the pcmc drives the dpra (drive pci read address) com- mand onto the hig [ 4:0 ] lines causing the lbxs to drive the pci address onto the host address bus. for a write cycle, the pcmc drives the dpwa (drive pci write address to cpu address bus) command on the hig [ 4:0 ] lines, also causing the lbxs to be- gin driving the host address bus. the pcmc then asserts eads y , initiating the snoop cycle to the cpu. the inv signal is asserted by the pcmc only during snoops due to pci master writes. inv re- mains negated during snoops due to pci master reads. if the snoop results in a hit to a modified line in the first level cache, the pentium processor as- serts hitm y . the pcmc samples the hitm y signal two clocks after the cpu samples eads y asserted to determine if the snoop hit in the first level cache. by this time the pcmc has completed an internal tag lookup to determine if the line is in the second level cache. since this snoop does not result in a write- back, the nopc command is driven on the hig [ 4:0 ] lines, causing the lbxs to tri-state the address bus. the sequence ends with ahold negation. if the pentium processor asserts ads y in the same clock as the pcmc asserts ahold, the pcmc will assert boff y in two cases. first, if the snoop cycle hits a modified line in the first level cache, the pcmc will assert boff y for 1 hclk to re-order the write- back around the currently sending cycle. second, if the snoop requires a write-back from the second lev- el cache, the pcmc will assert boff y to enable the write-back from the secondary cache srams. figure 35 depicts a snoop hit to a modified line in the first level cache due to a pci master memory read cycle. the snoop cycle begins when the pcmc asserts ahold causing the cpu to tri-state the address bus. the pcmc drives the dpra (drive pci read address) command on to the hig [ 4:0 ] lines causing the lbxs to drive the pci address onto the host ad- dress bus. the pcmc then asserts eads y , initiat- ing the snoop to the first level cache. inv is not asserted since this is a pci master read cycle. inv is only asserted with eads y when the snoop cycle is in response to a pci master write cycle. as the cpu is sampling eads y asserted, the pcmc latches the address. two clocks later, the pcmc completes the 93
82434LX/82434nx 290479 37 figure 35. snoop hit to modified line in first level cache, post memory and pci internal tag lookup to determine if the line is in the second level cache. in this instance, the snoop hits a modified line in the first level cache and misses in the second level cache. thus, the second level cache is not involved in the write-back cycle. the pcmc allows the lbxs to stop driving the address lines by driving nopc command on the hig [ 4:0 ] lines. the cpu then drives the write-back cycle onto the bus by asserting ads y and driving the write- back data on the data lines even though ahold is still asserted. the write-back into the lbx buffers occurs at a rate of 3-1-1-1. the pcmc drives pcmwfq on the hig [ 4:0 ] lines for one clock caus- ing the write data to be posted to both pci and main memory. for the next three clocks, the hig [ 4:0 ] lines are driven to pcmwnq, posting the final three qwords to both pci and main memory. a similar transfer from first level cache to the lbxs occurs when a snoop due to a pci master write hits a modified line in the first level cache. in this case, the write-back is transferred to the cpu-to-memory posted write buffer. if the line is in the second level cache, it is invalidated. the cycle is similar to the snoop cycle shown above with two exceptions. the pcmc drives the dpwa command on the hig [ 4:0 ] lines instead of the dpra command. during the four clocks where the pcmc drives brdy y active to the cpu, it also drives pcmwq on the hig [ 4:0 ] lines, causing the write to be posted to main memory. in both of the above cases where a write-back from the first level cache is required, ahold is asserted until the write-back is complete. if the cpu has be- gun a read cycle directed to pci and the snoop re- sults in a hit to a modified line in the first level cache, boff y is asserted for one clock to abort the cpu read cycle and re-order the write-back cycle before the read cycle. when a pci master read or write cycle hits a modi- fied line in the second level cache and either misses in the first level cache or hits an unmodified line in the first level cache, a write-back from the second level cache to the lbxs occurs. when a pci master write snoop hits an unmodified line in the second level cache and either misses in the first level cache or hits an unmodified line in the first level cache, no data transfer from the second level cache occurs. the line is simply invalidated. in the case of a pci master write cycle, the line is invalidated in both the first level and second level caches. in the case of a pci master memory read cycle, neither cache is in- validated. a pci master read from main memory which hits either a modified or unmodified line in the second level cache is shown in figure 36. 94
82434LX/82434nx 290479 38 figure 36. snoop hit to modified line in second level cache, store in pci read prefetch buffer the snoop cycle begins with the pcmc asserting ahold, causing the cpu to tri-state the host ad- dress bus. the pcmc drives the dpra command enabling the lbxs to drive the snoop address onto the host address bus. the pcmc asserts eads y . inv is not asserted in this case since the snoop cy- cle is in response to a pci master read cycle. if the snoop were in response to a pci master write cycle then inv would be asserted with eads y . two clocks after the cpu samples eads y active, the pcmc completes the internal tag lookup. in this case the snoop hit either an unmodified line or a modified line in the second level cache. since hitm y is inactive, the snoop did not hit in the first level cache. the pcmc then schedules a read from the second level cache to be written to the lbxs. when the cpu burst cycle completes the pcmc ne- gates the control signals to the second level cache and asserts cale opening the cache address latch and allowing the snoop address to flow through to the srams. the second level cache executes a read sequence which completes at 3-2-2-2 in the case of standard srams and 3-1-1-1 in the case of burst srams. during all snoop cycles where a write- back from the second level cache is required, boff y is asserted throughout the write-back cycle. this prevents the deadlock that would occur if the cpu is in the middle of a non-postable write and the data bus is required for the second level cache write-back. when using burst srams, the read from the srams follows the pentium processor burst order. however, the memory to pci read prefetch buffer in the lbxs is organized as a fifo and cannot accept data out of order. the swb0, swb1, swb2 and swb3 com- mands are used to write data into the buffer in as- cending order. in the above example, the pci master requests a data item which hits qword 0 in the cache, thus ca [ 4:3 ] count through the following se- quence: 0, 1, 2, 3 (00, 01, 10, 11). if the pci mas- 95
82434LX/82434nx ter requests a data item that hits qword 1, the swb0 command is sent via the hig [ 4:0 ] lines to store qword 1in the first buffer location. the next read from the cache is not in ascending order, thus a nopc is sent on the hig [ 4:0 ] lines. this qword is not posted in the buffer. the next read from the cache is to qword 3. swb2 is sent on the hig [ 4:0 ] lines. the final read from the cache is qword 2. swb1 is sent on the hig [ 4:0 ] lines. thus, qword 1 is placed in entry 0 in the buffer, qword 2 is placed in entry 1 in the buffer and qword 3 is placed in entry 2 in the buffer. the ordering between the qwords read from the cache and the hig [ 4:0 ] commands when using burst srams is summarized in table 9. table 9. hig [ 4:0 ] command sequence for second level cache to pci master read prefetch buffer transfer burst order hig [ 4:0 ] command from cache sequence 0, 1, 2, 3 swb0, swb1, swb2, swb3 1, 0, 3, 2 swb0, nopc, swb2, swb1 2, 3, 0, 1 swb0, swb1, nopc, nopc 3, 2, 1, 0 swb0, nopc, nopc, nopc when using standard asynchronous srams, the read from the srams occurs in a linear burst order. thus, caa [ 4:3 ] and cab [ 4:3 ] count in a linear burst order and the store write buffer commands are sent in linear order. the burst ends at the cache line boundary and does not wrap around and continue with the beginning of the cache line. a pci master write cycle which hits a modified line in the second level cache and either hits an unmodified line in the first level cache or misses in the first level cache will also cause a transfer from the second level cache to the lbxs. in this case, the read from the srams is posted to main memory and the line is invalidated in the second level cache. the cycle would differ only slightly from the above cycle. inv would be asserted with eads y . instead of the dpra command, the pcmc would use the dpwa command to drive the snoop address onto the host address bus. the write would be posted to the dram, thus the pcmc would drive the pcmwq command on the hig [ 4:0 ] lines to post the write to dram. a snoop cycle can result in a write-back from the first level cache to both the second level and lbxs in the case of a pci master read cycle which hits a modified line in the first level cache and hits either a modified or unmodified line in the second level cache. the line is written to both the second level cache and the memory to pci read prefetch buffer. the cycle is shown in figure 37. 96
82434LX/82434nx 290479 39 figure 37. snoop hit to modified line in first level cache, write-back from first level cache to second level cache and send to pci this cycle is shown for the case of a second level cache with burst srams. in this case, as it com- pletes the second level cache tag lookup, the pcmc samples hitm y active. the write-back is written to the second level cache and simultaneously stored in the memory to pci prefetch buffer. in the case shown in figure 33, the pci master requests a data item which is contained in qword 0 of the cache line. note that a write-back from the first level cache al- ways starts with qword 0 and finishes with qword 3. thus the hig [ 4:0 ] lines are sequenced through the following order: swb0, swb1, swb2, swb3. if the pci master requests a data item which is contained in qword 1, the hig [ 4:0 ] lines sequence through the following order: nopc, swb0, swb1, swb2. if the pci master requests a data item which is contained in qword 2, the hig [ 4:0 ] lines sequence through the following order: nopc, nopc, swb0, swb1. if the pci master requests a data item which is contained in qword 3, the hig [ 4:0 ] lines sequence through the following order: nopc, nopc, nopc, swb0. ahold is negated after the write-back cycle is com- plete. if the cpu has begun a read cycle directed to pci and the snoop results in a hit to a modified line in the first level cache, boff y is asserted for one clock to abort the cpu read cycle and re-order the write- back cycle before the pending read cycle. 97
82434LX/82434nx 5.1.5 flush, flush acknowledge and write-back special cycles there are three special cycles that affect the second level cache, flush, flush acknowledge, and write- back. if the processor executes an invd instruction, it will invalidate all unmodified first level cache lines and issue a flush special cycle. if the processor exe- cutes a wbinvd instruction, it will write back all modified first level cache lines, invalidate the first level cache, and issue a write-back special cycle fol- lowed by a flush special cycle. if the pentium proc- essor flush y pin is asserted, the cpu will write- back all modified first level cache lines, invalidate the first level cache, and issue a flush acknowledge special cycle. the second level cache behaves the same way in response to the flush special cycle and flush ac- knowledge special cycle. each tag is read and the valid and modified bits are examined. if the line is both valid and modified it is written back to main memory and the valid bit for that line is reset. all valid and unmodified lines are simply marked invalid. the pcmc advances to the next tag when all lines within the current sector have been examined. brdy y is returned to the pentium processor after all modified lines in the second level cache have been written back to main memory and all of the valid bits for the second level cache are reset. the sequence of write-back cycles will only be interrupt- ed to service a pci master cycle. the write-back special cycle is ignored by the pcmc because all modified lines will be written back to main memory by the following flush special cycle. upon decoding a write-back special cycle, the pcmc simply returns brdy y to the pentium proc- essor. 5.2 82434nx cache the 82434nx pcmc integrates a high performance write-back second level cache controller, tag ram and a full first and second level cache coherency mechanism. the cache is either 256 kbytes or 512 kbytes using either synchronous burst srams or standard asynchronous srams. parity on the data srams is optional. the cache uses a write- back write policy. write-through mode is not support- ed. the 82434nx pcmc supports a direct mapped sec- ondary cache. the pcmc contains 4096 tags. each tag represents a sector in the cache. if the cache is 512 kb, each sector contains four cache lines. if the cache is 256 kb, each sector contains two cache lines. valid and modified bits are kept on a per line basis. the 82434nx tag ram is 1 bit wider than the 82434LX tag ram. the pcmc can be configured to cache main memo- ry on read cycles even when cache y is not assert- ed. when bit 4 in the secondary cache control reg- ister (offset 52h) is set to 1, all accesses to main memory, except those to smm memory or any range marked non-cacheable via the pam registers, are cached in the secondary cache. accesses with cache y asserted result in a line fill in both the first and second level cache while accesses with cache y negated result in a line fill only in the sec- ond level cache. when bit 4 in the scc register is set to 0, only access with cache y asserted can generate a first and second level cache line fill. when a halt or stop grant special cycle is detected from the cpu, the 82434nx pcmc places the sec- ond level cache into the low power stand-by mode by deselecting the srams and then generates the corresponding special cycle on pci. (i.e., if the cpu cycle was a halt special cycle then the pcmc gener- ates a halt special cycle on pci and if the cpu cycle is a stop grant special cycle the pcmc generates a stop grant special cycle on pci). when a burst sram secondary cache is implement- ed, bit 2 of the secondary cache control register (offset 52h) is used to select between 82434LX sram connectivity and the new 82434nx sram connectivity. when set to 0, the secondary cache interface is in 82430-compatible mode. (i.e., the four low order address lines on the srams are connect- ed to caa/b [ 6:3 ] on the pcmc. when set to 1, sec- ond level cache stand-by is enabled and no latch is used between the host cpu address lines and the sram address lines. all of the sram address lines are then connected directly to the cpu address lines. write-back addresses are driven by the pcmc over the host address lines. when a standard sram secondary cache is implemented, bit 2 of the sec- ondary cache control register (offset 52h) is used to enable second level cache stand-by. the default value of this bit is 0. figure 38 and figure 41 show the connections be- tween the pcmc and the external cache data srams and latch for the case of an asynchronous sram cache. 98
82434LX/82434nx 290479 40 note: in this mode, srams which internally gate adsp y with cs y must be used. figure 38. 512 kbyte secondary cache, synchronous burst sram (82434nx) 99
82434LX/82434nx 290479 41 figure 39. 512 kbyte secondary cache, standard dual-byte-select (asynch) sram, 50, 60 & 66 mhz figure 38 depicts the pcmc connections to a 512 kbyte burst sram secondary cache when the pcmc is configured for 50, 60, or 66 mhz operation. host address lines ha [ 18:3 ] are connected directly to the sram address lines, a [ 15:0 ] . ads y from the cpu is connected to adsp y on the srams. cadv0 y implements the address advance (adv y ) functionality. a new signal, ccs y , is multiplexed onto the cadv1 y pin. when bit 2 in the scc regis- ter is set to 1, srams containing logic which gates adsp y with cs y must be used. when negated, ccs y prevents the srams from latching a new ad- dress due to a pipelined ads y from the cpu during cache line fills. note that, unlike the burst sram configuration with the 82430 pciset, no external latch is used between the cpu address bus and the sram address lines. the sram connectivity bit (bit 2) in the secondary cache control register (offset 52h) must be set to 1 when using this cache configu- ration. if the tag lookup results in a miss in the cache and the sector to be replaced contains one or more mod- ified lines, the pcmc drives the write-back address from the a [ 18:3 ] lines on the host bus. although not used in the write-back, a [ 31:19 ] (or a [ 31:18 ] in the case of a 256 kb cache) are driven to valid logic levels by the pcmc. figure 39 depicts the 82434nx pcmc connections to a 512 kbyte standard asynchronous sram sec- ondary cache. figure 40 depicts the 82434nx con- nections to a 256 kbyte asynchronous sram sec- ondary cache. host address lines ha [ 18:7 ] are driven through an external latch to form the upper sram address lines, ca [ 18:7 ] .ca [ 6:3 ] are driven from the pcmc. figure 41 depicts the 82434nx pcmc connections to a 512 kbyte stan- dard sram secondary cache with dual-write-enable srams. 100
82434LX/82434nx 290479 42 figure 40. 82434nx connections to 256 kbyte cache with standard sram 101
82434LX/82434nx 290479 43 figure 41. 82434nx connections to 512 kbyte cache with standard sram 5.2.1 cycle latency summary (82434nx) table 10 and table 11 summarize the clock laten- cies for cpu memory cycles which hit in the second- ary cache. table 10. secondary cache latencies with synchronous burst sram cycle type 50, 60 and 66 mhz burst read 3-1-1-1 burst write 3-1-1-1 single read 3 single write 3 pipelined back-to-back 3-1-1-1-1-1-1-1 burst reads burst read followed 3-1-1-1-2 by pipelined write table 11. secondary cache latencies with standard asynchronous sram (82434nx) cycle type 50, 60 and 66 mhz burst read 3-2-2-2 burst write 4-2-2-2 single read 3 single write 4 pipelined back-to-back 3-2-2-2-3-2-2-2 burst reads burst read followed 3-2-2-2-4 by pipelined write 102
82434LX/82434nx the 60 mhz and 66 mhz asynchronous sram la- tencies require 15 ns and 12 ns srams, respective- ly. the 82434nx pcmc supports asynchronous srams at 50 mhz. the 50 mhz (1 wait-state) tim- ings require 20 ns srams. the burst srams speeds for 66 mhz, 60 mhz and 50 mhz operation are 8 ns, 9 ns, and 13 ns clock-to-output valid into a 0 pf test load. the sram access times listed in this paragraph are recommendations. actual access time requirements are a function of system board layout and routing and should be validated with elec- trical simulation. 5.2.2 standard sram cache cycles (82434nx) at 50, 60 and 66 mhz, the timing of the second level cache interface with standard asynchronous srams is identical to the timing in the 82430lx pciset. compared to the 82434LX second level cache, one additional connection can be made from the pcmc to the srams. the ccs [ 1:0 ] y pins, in the case of asynchronous srams, are multiplexed onto the cadv [ 1:0 ] y pins. these are then connected to the sram cs y pins. the two copies are functionally identical. the two copies are provided for timing rea- sons. these pins allow the pcmc to deselect the srams, putting them into standby mode. when a halt special cycle or a stop grant special cycle is detected from the cpu, the pcmc negates ccs [ 1:0 ] y , placing the srams into the low power standby mode. the pcmc then generates a halt or stop grant special cycle on pci. 5.2.3 second level cache standby when the pcmc detects a halt or stop grant special cycle from the cpu, it first places the second level cache into the low power stand-by mode by dese- lecting the srams and then generates a halt or stop grant special cycle on pci. with a standard sram secondary cache, a halt or stop grant special cycle from the cpu causes the pcmc to negate ccs [ 1:0 ] y , deselecting the srams and placing them in a low power standby mode. when the cache is in stand-by mode, the first bus cycle from the cpu brings the cache out of stand-by and into active mode, enabling the srams to service the cycle in the case of a hit to the cache. the pcmc asserts ccs [ 1:0 ] y as a propagation de- lay from the falling edge of ads y . ccs [ 1:0 ] y are then left asserted until the next halt or stop grant special cycle is occurs. when exiting the powerdown state, the pcmc ignores the secondary cache lea- doff wait-states bit and executes a 3-2-2-2 read or 4-2-2-2 write in order to allow the srams time to power up. in the case of a read cycle, coe [ 1:0 ] y are asserted in clock two as in the case of ordinary read cycles. when the srams are powered down, the pcmc as- serts ccs [ 1:0 ] y when performing a snoop cycle, regardless of whether the cycle hits in the second level cache. the pcmc then negates ccs y after the snoop cycle is complete. with a burst sram secondary cache, a halt or stop grant special cycle from the cpu causes the pcmc to negate ccs y and assert cads [ 1:0 ] y , deselect- ing the srams, placing them in a low power standby mode. ccs y is then asserted and is left asserted by the pcmc. thus, when the first cycle is driven from the cpu, the srams sample adsp y and cs y ac- tive, placing them in active mode and initiating the first access. if the srams are required to service a snoop, they are brought out of power-down when the pcmc as- serts cads [ 1:0 ] y . the pcmc always asserts cads [ 1:0 ] y with ccs y negated after a snoop cy- cle is complete, regardless of whether the srams were powered down prior to the snoop cycle. 5.2.4 snoop cycles for snoop operations, refer to section 5.1, 82434LX cache. 5.2.5 flush, flush acknowledge, and write-back special cycles for flush, flush acknowledge, and write-back special cycles, refer to section 5.1, 82434LX cache. 103
82434LX/82434nx 6.0 dram interface this section describes the dram interface for the 82434LX dram interface (section 6.1) and the 82434nx dram interface (section 6.2). the differ- ences are in the following areas: 1. increased maximum dram memory size to 512 mbytes. an extra address line (ma11) has been added to the 82434nx. 2. two additional ras y lines for a total of eight (ras [ 0:7 ] y . 3. addition of 50 mhz host-bus optimized dram timing sets. thus, the 82434LX supports 60 and 66 mhz frequencies and the 82434nx supports 50, 60, and 66 mhz. 6.1 82434LX dram interface the 82434LX pcmc integrates a high performance dram controller supporting from 2 192 mbytes of main memory. the pcmc generates the ras y , cas y ,we y and multiplexed addresses for the dram array, while the data path to dram is provid- ed by two 82433lx lbxs. the dram controller in- terface is fully configurable through a set of control registers. complete descriptions of these registers are given in section 3.0, register description. a brief overview of the registers which configure the dram interface is provided in this section. the 82434LX controls a 64-bit memory array (72-bit including parity) ranging in size from 2 mbytes up to 192 mbytes using industry standard 36-bit wide memory modules with fast page-mode drams. both single- and double-sided simms are supported. the eleven multiplexed address lines, ma [ 10:0 ] allow the pcmc to support 256k x 36, 1m x 36, and 4m x 36 simms. the pcmc has six ras y lines en- abling the support of up to six rows of dram. eight cas y lines allow byte control over the array during read and write operations. the pcmc supports 70 and 60 ns drams. the pcmc dram interface is synchronous to the cpu clock and supports page mode accesses to efficiently transfer data in bursts of four qwords. the dram interface of the pcmc is configured by the dram control mode register (offset 57h) and the six dram row boundary (drb) registers (off- sets 60h 65h). the dram control mode register contains bits to configure the dram interface for ras y modes and refresh options. in addition, dram parity error reporting and system manage- ment ram space can be enabled and disabled. when system management ram is enabled, if smiact y from the pentium processor is not assert- ed, all cpu read and write accesses to smm memo- ry are directed to pci. the smram space register at configuration space offset 72h provides additional control over the smram space. the six drb regis- ters define the size of each row in the memory array, enabling the pcmc to assert the proper ras y line for accesses to the array. cpu-to-memory write posting and read-around-write operations are enabled and disabled via the host read/write buffer control register (offset 53h). pci-to-memory write posting is enabled and dis- abled via the pci read/write buffer control regis- ter (offset 54h). pci master reads from main memory always result in the pcmc and lbxs reading the requested data and prefetching the next seven dwords. seven programmable attribute map (pam) regis- ters (offsets 59h 5fh) are used to specify the cacheability and read/write status of the memory space between 512 kbytes and 1 mbyte. each pam register defines a specific address area enabling the system to selectively mark specific memory ranges as cacheable, read-only, write-only, read/ write or disabled. when a memory range is disabled, all cpu accesses to that range are directed to pci. two other registers also affect the dram interface, the memory space gap register (offsets 78h 79h) and the frame buffer range register (offsets 7ch 7fh). the memory space gap register is used to place a logical hole in the memory space between 1 mbyte to 16 mbytes to accommodate memory mapped isa boards. the frame buffer range reg- ister, is used to map a linear frame buffer into the memory space gap or above main memory. when enabled, accesses to these ranges are never direct- ed to the dram interface, but are always directed to pci. 104
82434LX/82434nx 6.1.1 dram configurations figure 42 illustrates a 12-simm configuration which supports single-sided simms. a row in the dram array is made up of two simms which share a com- mon ras y line. simm0 and simm1 are connected to ras0 y and therefore, comprise row 0. simm10 and simm11 form row 5. within any given row, the two simms must be the same size. among the six rows, simm densities can be mixed in any order. that is, there are no restrictions on the ordering of simm densities among the six rows. the low order lbx (lbxl) is connected to byte lanes 5, 4, 1, and 0 of the host and memory data buses, and the lower two bytes of the pci ad bus. the high order lbx (lbxh) is connected to byte lanes 7, 6, 3, and 2 of the host and memory data buses, and the upper two bytes of the pci ad bus. thus, simms connected to lbxl are connected to cas [ 5:4,1:0 ] y and simms connected to lbxh are connected to cas [ 7:6, 3:2 ] y . the ma [ 10:0 ] and we y lines are externally buff- ered to drive the large capacitance of the memory array. three buffered copies of the ma [ 10:0 ] and we y signals are required to drive the six row array. figure 43 illustrates a 6-simm configuration that supports either single- or double-sided simms. in this configuration, single- and double-sided simms can be mixed. for example, if single-sided simms are installed into the sockets marked simm0 and simm1, then ras0 y is connected to the simms and ras1 y is not connected. row 0 is then popu- lated and row 1 is empty. two double-sided simms could then be installed in the sockets marked simm2 and simm3, populating rows 2 and 3. 6.1.2 dram address translation the 82434LX multiplexed row/column address to the dram memory array is provided by the ma [ 10:0 ] signals. the ma [ 10:0 ] bits are derived from the host address bus as defined by table 12. ma [ 10:0 ] are translated from the host address a [ 24:3 ] for all memory accesses, except those tar- geted to memory that has been remapped as a re- sult of the creation of a memory space gap in the lower extended memory area. in the case of a cycle targeting remapped memory, the least significant bits come directly from the host address, while the more significant bits depend on the memory space gap start address, gap size, and the size of main memory. table 12. dram address translation memory address, 10 9 876543210 ma [ 10:0 ] row address a24 a22 a20 a19 a18 a17 a16 a15 a14 a13 a12 column address a23 a21 a11 a10 a9 a8 a7 a6 a5 a4 a3 105
82434LX/82434nx 290479 51 note: the figure shows the connections for the 82434LX. for the 82434nx, there are two additional ras lines (ras [ 7:6 ] y ) and one additional address line (ma11). figure 42. 82434LX dram configuration supporting single-sided simms 106
82434LX/82434nx 290479 52 note: the figure shows the connections for the 82434LX. for the 82434nx, there are two additional ras lines (ras [ 7:6 ] y ) and one additional address line (ma11). figure 43. 82434LX dram configuration supporting single- or double-sided simms 107
82434LX/82434nx 6.1.3 cycle timing summary the 82434LX pcmc dram performance is summa- rized in table 13 for all cpu read and write cycles. table 13. cpu to dram performance summary burst, single, cycle type x-4-4-4 x-4-4-4 timing timing read page hit 7-4-4-4 7 read row miss 11-4-4-4 11 read page miss 14-4-4-4 14 posted write, wt l2 3-1-1-1 3 posted write, wb l2 4-1-1-1 4 write page hit 12-4-4-4 12 write row miss 13-4-4-4 13 write page miss 16-4-4-4 16 0-active ras y 10-4-4-4 10 mode read 0-active ras y 12-4-4-4 12 mode write cpu writes to the cpu-to-memory posted write buffer are completed at 3-1-1-1 when the second level cache is configured for write-through mode and 4-1-1-1 when the cache is configured for write-back mode. table 14 shows the refresh performance in cpu clocks. table 14. refresh cycle performance refresh hidden ras y only cas y before type refresh refresh ras y single 12 13 14 burst of four 48 52 56 6.1.4 cpu to dram bus cycles this section describes the cpu-to-dram cycles for the 82434LX. 6.1.4.1 read page hit figure 44 depicts a cpu burst read page hit from dram. the 82434LX pcmc decodes the cpu ad- dress as a page hit and drives the column address onto the ma [ 10:0 ] lines. cas [ 7:0 ] y are then assert- ed to cause the drams to latch the column address and begin the read cycle. cmr (cpu memory read) is driven on the hig [ 4:0 ] lines to enable the memory data to host data path through the lbxs. the pcmc advances the ma [ 1:0 ] lines through the pentium processor burst order, negating and asserting cas [ 7:0 ] y to read each qword. the host data is latched on the falling edge of mdle, when cas [ 7:0 ] y are negated. the latch is opened again when mdle is sampled asserted by the lbxs. the lbxs tri-state the host data bus when hig [ 4:0 ] change to nopc and mdle rises. a single read page hit from dram is similar to the first read of this sequence. the hig [ 4:0 ] lines are driven to nopc when brdy y is asserted. 108
82434LX/82434nx 290479 53 figure 44. burst dram read cycle-page hit 109
82434LX/82434nx 6.1.4.2 read page miss figure 45 depicts a cpu burst read page miss from dram. the 82434LX decodes the cpu address as a page miss and switches from initially driving the column address to driving the row address on the ma [ 10:0 ] lines. ras y is then negated to precharge the drams and then asserted to cause the drams to latch the new row address. the pcmc then switches the ma [ 10:0 ] lines to drive the column ad- dress and asserts cas [ 7:0 ] y . cmr (cpu memory read) is driven on the hig [ 4:0 ] lines to enable the memory data to host data path through the lbxs. the pcmc advances the ma [ 1:0 ] lines through the pentium processor burst order, negating and assert- ing cas [ 7:0 ] y to read each qword. the host data is latched on the falling edge of mdle, when cas [ 7:0 ] y are negated. the latch is opened again when mdle is sampled asserted by the lbxs. the lbxs tri-state the host data bus when hig [ 4:0 ] change to nopc and mdle rises. a single read page miss from dram is similar to the first read of this sequence. the hig [ 4:0 ] lines are driven to nopc when brdy y is asserted. 290479 54 figure 45. dram read cycle-page miss 110
82434LX/82434nx 6.1.4.3 read row miss figure 46 depicts a cpu burst read row miss from dram. the 82434LX decodes the cpu address as a row miss and switches from initially driving the col- umn address to driving the row address on the ma [ 10:0 ] lines. the ras y signal that was asserted is negated and the ras y for the currently accessed row is asserted. the pcmc then switches the ma [ 10:0 ] lines to drive the column address and as- serts cas [ 7:0 ] y . cmr (cpu memory read) is driv- en on the hig [ 4:0 ] lines to enable the memory data to host data path through the lbxs. the pcmc ad- vances the ma [ 1:0 ] lines through the pentium proc- essor burst order, negating and asserting cas [ 7:0 ] y to read each qword. the host data is latched on the falling edge of mdle, when cas [ 7:0 ] y are negated. the latch is opened again when mdle is sampled asserted by the lbxs. the lbxs tri-state the host data bus when hig [ 4:0 ] change to nopc and mdle rises. a single read row miss from dram is similar to the first read of this sequence. the hig [ 4:0 ] lines are driven to nopc when brdy y is asserted. 290479 55 figure 46. burst dram read cycle-row miss 111
82434LX/82434nx 6.1.4.4 write page hit figure 47 depicts a cpu burst write page hit from dram. the 82434LX decodes the cpu write cycle as a dram page hit. the hig [ 4:0 ] lines are driven to pcmwq to post the write to the lbxs. in the fig- ure, the write cycle is posted to the cpu-to-memory posted write buffer at 4-1-1-1. the write is posted at 4-1-1-1 when the second level cache is configured for a write-back policy. the write is posted to dram at 3-1-1-1 when the second level cache is config- ured for a write-through policy. when the cycle is decoded as a page hit, the pcmc asserts we y and drives the rcmwq command on mig [ 2:0 ] to enable the lbxs to drive the first qword of the write onto the memory data lines. memdrv is then driven to cause the lbxs to continue to drive the first qword for three more clocks. cas [ 7:0 ] y are then negated and asserted to perform the writes to the drams as the ma [ 1:0 ] lines advance through the pentium processor burst order. a single write is similar to the first write of the burst sequence. mig [ 2:0 ] are driven to nopm in the clock after cas [ 7:0 ] y are asserted. 290479 56 figure 47. burst dram write cycle-page hit 112
82434LX/82434nx 6.1.4.5 write page miss figure 48 depicts a cpu burst write page miss to dram. the 82434LX decodes the cpu write cycle as a dram page miss. the hig [ 4:0 ] lines are driven to pcmwq to post the write to the lbxs. in the fig- ure, the write cycle is posted to the cpu-to-memory posted write buffer at 4-1-1-1. the write is posted at 4-1-1-1 when the second level cache is configured for a write-back policy. the write is posted to dram at 3-1-1-1 when the second level cache is config- ured for a write-through policy. when the cycle is decoded as a page miss, the pcmc switches the ma [ 10:0 ] lines from the column address to the row address and asserts we y . the pcmc drives the rcmwq command on mig [ 2:0 ] to enable the lbxs to drive the first qword of the write onto the memory data lines. memdrv is then driven to cause the lbxs to continue to drive the first qword. the ras y signal for the currently decoded row is negated to precharge the drams. ras y is then asserted to cause the drams to latch the row address. the pcmc then switches the ma [ 10:0 ] lines to the col- umn address and asserts cas [ 7:0 ] y to initiate the first write. cas [ 7:0 ] y are then negated and assert- ed to perform the writes to the drams as the ma [ 1:0 ] lines advance through the pentium proces- sor burst order. a single write is similar to the first write of the burst sequence. mig [ 2:0 ] are driven to nopm in the clock after cas [ 7:0 ] y are asserted. 290479 57 figure 48. burst dram write cycle-page miss 113
82434LX/82434nx 6.1.4.6 write row miss figure 49 depicts a cpu burst write row miss to dram. the 82434LX decodes the cpu write cycle as a dram row miss. the hig [ 4:0 ] lines are driven to pcmwq to post the write to the lbxs. in the fig- ure, the write cycle is posted to the cpu-to-memory posted write buffer at 4-1-1-1. the write is posted at 4-1-1-1 when the second level cache is configured for a write-back policy. the write is posted to dram at 3-1-1-1 when the second level cache is config- ured for a write-through policy. when the cycle is decoded as a row miss, the pcmc negates the al- ready active ras y signal, switches the ma [ 10:0 ] lines from the column address to the row address and asserts the ras y signal for the currently de- coded row. the pcmc asserts we y and drives the rcmwq command on mig [ 2:0 ] to enable the lbxs to drive the first qword of the write onto the memory data lines. memdrv is then driven to cause the lbxs to continue to drive the first qword. the pcmc then switches the ma [ 10:0 ] lines to the column ad- dress and asserts cas [ 7:0 ] y to initiate the first write. cas [ 7:0 ] y are then negated and asserted to perform the writes to the drams as the ma [ 1:0 ] lines advance through the pentium processor burst order. a single write is similar to the first write of the burst sequence. mig [ 2:0 ] are driven to nopm in the clock after cas [ 7:0 ] y are asserted. 290479 58 figure 49. burst dram write cycle-row miss 114
82434LX/82434nx 6.1.4.7 read cycle, 0-active ras y mode when in 0-active ras y mode, every cpu cycle to dram results in a ras y and cas y sequence. ras y is always negated after a cycle completes. figure 50 depicts a cpu burst read cycle from dram where the 82434LX is configured for 0-active ras y mode. when in 0-active ras y mode, the pcmc defaults to driving the row address on the ma [ 10:0 ] lines. the pcmc asserts the ras y signal for the currently decoded row causing the drams to latch the row address. the pcmc then switches the ma [ 10:0 ] lines to drive the column address and as- serts cas [ 7:0 ] y . cmr (cpu memory read) is driv- en on the hig [ 4:0 ] lines to enable the memory data to host data path through the lbxs. the pcmc ad- vances the ma [ 1:0 ] lines through the pentium proc- essor burst order, negating and asserting cas [ 7:0 ] y to read each qword. the host data is latched on the falling edge of mdle, when cas [ 7:0 ] y are negated. the latch is opened again when mdle is sampled asserted by the lbxs. the lbxs tri-state the host data bus when hig [ 4:0 ] change to nopc and mdle rises. a single read row miss from dram is similar to the first read of this sequence. the hig [ 4:0 ] lines are driven to nopc when brdy y is asserted. ras y is negated with cas [ 7:0 ] y . 290479 59 figure 50. burst dram read cycle, 0-active ras y mode 115
82434LX/82434nx 6.1.4.8 write cycle, 0-active ras y mode when in 0-active ras y mode, every cpu cycle to dram results in a ras y and cas y sequence. ras y is always negated after a cycle completes. figure 51 depicts a cpu burst write cycle to dram where the 82434LX is configured for 0-active ras y mode. the hig [ 4:0 ] lines are driven to pcmwq to post the write to the lbxs. in the figure, the write cycle is posted to the cpu-to-memory posted write buffer at 4-1-1-1. the write is posted at 4-1-1-1 when the second level cache is configured for a write-back policy. the write is posted to dram at 3-1-1-1 when the second level cache is configured for a write-through policy. when in 0-active ras y mode, the pcmc defaults to driving the row address on the ma [ 10:0 ] lines. the pcmc asserts the ras y signal for the currently decoded row causing the drams to latch the row address. the pcmc asserts we y and drives the rcmwq command on mig [ 2:0 ] to enable the lbxs to drive the first qword of the write onto the memory data lines. memdrv is then driven to cause the lbxs to continue to drive the first qword. the pcmc then switches the ma [ 10:0 ] lines to the column address and asserts cas [ 7:0 ] y to initiate the first write. cas [ 7:0 ] y are then negated and asserted to perform the writes to the drams as the ma [ 1:0 ] lines advance through the pentium processor burst order. a single write is similar to the first write of the burst sequence. mig [ 2:0 ] are driven to nopm in the clock after cas [ 7:0 ] are asserted. 290479 60 figure 51. burst dram write cycle, 0-active ras y mode 116
82434LX/82434nx 6.1.5 refresh the refresh of the dram array can be performed by either using ras y -only or cas y -before-ras y re- fresh cycles. when programmed for cas y -before- ras y refresh, hidden refresh cycles are initiated when possible. ras y only refresh can be used with any type of second level cache configuration (i.e., no second level cache is present, or either a burst sram or standard sram second level cache is im- plemented). cas y -before-ras y refresh can be en- abled when either no second level cache is present or a burst sram second level cache is implement- ed. cas y -before-ras y refresh should not be used when a standard sram second level cache is imple- mented. the timing of internally generated refresh cycles is derived from hclk and is independent of any expansion bus refresh cycles. the dram controller contains an internal refresh timer which periodically requests the refresh control logic to perform either a single refresh or a burst of four refreshes. the single refresh interval is 15.6 m s. the interval for burst of four refreshes is four times the single refresh interval, or 62.4 m s. the pcmc is configured for either single or burst of four refresh and either ras y -only or cas y -before-ras y re- fresh via the dram control register (offset 57h). to minimize performance impact, refresh cycles are partially deferred until the dram interface is idle. the deferment of refresh cycles is limited by the dram maximum ras y low time of 100 m s. refresh cycles are initiated such that the ras y maximum low time is never violated. hidden refresh cycles are run whenever all eight cas y lines are active when the refresh cycle is in- ternally requested. normal cas y -before-ras y re- fresh cycles are run whenever the dram interface is idle when the refresh is requested, or when any sub- set of the cas y lines is inactive as the refresh is internally requested. to minimize the power surge associated with re- freshing a large dram array the dram interface staggers the assertion of the ras y signals during both cas y -before-ras y and ras y -only refresh cycles. the order of ras y edges is dependent on which ras y was most recently asserted prior to the refresh sequence. the ras y that was active will be the last to be activated during the refresh sequence. all ras [ 5:0 ] y lines are negated at the end of re- fresh cycles, thus, the first dram cycle after a re- fresh sequence is a row miss. 6.1.5.1 ras y -only refresh-single figure 52 depicts a ras y -only refresh cycle when the 82434LX is programmed for single refresh cy- cles. the diagram shows a cpu read cycle complet- ing as the refresh timing inside the pcmc generates a refresh request. the refresh address is driven on the ma [ 10:0 ] lines. since the cpu cycle was to row 0, ras0 y is negated. ras1 y is the first to be as- serted. ras2 y through ras5 y are then asserted sequentially while ras0 y is driven high, precharg- ing the drams in row 0. ras0 y is then asserted after ras5 y . each ras y line is asserted for six host clocks. 117
82434LX/82434nx 290479 61 figure 52. ras y only refresh-single 118
82434LX/82434nx 6.1.5.2 cas y -before-ras y refresh-single figure 53 depicts a cas y -before-ras y refresh cy- cle when the 82434LX is programmed for single re- fresh cycles. the diagram shows a cpu read cycle completing as the refresh timing inside the pcmc generates a refresh request. the cpu read cycle is less than a qword, therefore a hidden refresh is not initiated. after the cpu read cycle completes, all of the ras y and cas y lines are negated. the pcmc then asserts cas [ 7:0 ] y and then sequentially as- serts the ras y lines, starting with ras1 y since ras0 y was the last ras y line asserted. each ras y line is asserted for six clocks. 290479 62 figure 53. cas y -before-ras y refresh-single 119
82434LX/82434nx 6.1.5.3 hidden refresh-single figure 54 depicts a hidden refresh cycle which takes place after a dram read page hit cycle. the dia- gram shows a cpu read cycle completing as the refresh timing inside the 82434LX generates a re- fresh request. the cpu read cycle is an entire qword, therefore a hidden refresh is initiated. after the cpu read cycle completes, ras y is negated, but all eight cas y lines remain asserted. the pcmc then sequentially asserts the ras y lines, starting with ras1 y since ras0 y was the last ac- tive ras y line. each ras y line is asserted for six clocks. 290479 63 figure 54. hidden refresh-single 120
82434LX/82434nx 6.2 82434nx dram interface this section describes the 82434nx dram inter- face. changes in the 82430nx pciset from the 82430 pciset include: 1. increased maximum dram memory size to 512 mbytes. the 82430nx pciset increases the maximum memory array size from 192 mbytes to 512 mbytes. 2. two additional row address lines (ras [ 7:6 ] y ) for a total of eight (ras [ 7:0 ] y ). 3. addition of 50 mhz host-bus optimized dram timing sets. 4. three additional registers are added to support the increased memory sizedram row boundary registers 6 and 7 (drb [ 7:6 ] ) and the dram row boundary extension (drbe) register. 5. modified ma [ 11:0 ] timing to provide more ma [ 11:0 ] setup time to cas [ 7:0 ] y assertion. 6.2.1 dram address translation the ma [ 11:0 ] lines are translated from the host ad- dress lines a [ 26:3 ] for all memory accesses, except those targeted to memory that has been remapped as a result of the creation of a memory space gap in the lower extended memory area. in the case of a cycle targeting remapped memory, the least signifi- cant bits come directly from the host address, while the more significant bits depend on the memory space gap start address, gap size, and the size of main memory. table 15. dram address translation memory address 11 10 9876543210 ma [ 11:0 ] column address a25 a23 a21 a11 a10 a9 a8 a7 a6 a5 a4 a3 row address a26 a24 a22 a20 a19 a18 a17 a16 a15 a14 a13 a12 121
82434LX/82434nx 6.2.2 cycle timing summary the 82434nx pcmc dram performance for 50 mhz host bus clock is summarized in table 13 for all cpu read and write cycles. the 60/66 mhz ma [ 11:0 ] timings when in x-4-4-4 mode have one difference from the 82434LX ma [ 11:0 ] timings. the ma lines switch to the next address in the burst se- quence one clock sooner than in the 82434LX, pro- viding more ma [ 11:0 ] setup time to cas [ 7:0 ] y as- sertion. the 60/66 mhz dram timings for write cy- cles have been improved by 1 clock for all leadoffs. the 50 mhz timings shown below are selected by hof e 00, dbt e 11, rws e 0 and cws e 0. table 16. cpu to dram performance summary for 50 mhz host bus clock cycle type x-3-3-3 timing (1) read (page hit/row miss/ 6/10/12-3-3-3 page miss) posted write 4-1-1-1 write (page hit/row miss/ 10/11/13-3-3-3 page miss) 0-active ras y 9-3-3-3 mode reads 0-active ras y 9-3-3-3 mode writes notes: 1. single cycle timings are identical to these leadoff timings. table 17. refresh cycle performance (independent of cpu frequency) refresh hidden ras y only cas y - type refresh refresh before- ras y single 16 17 18 burst of four 64 68 72 6.2.3 cpu to dram bus cycles in this section, all timing diagrams are for 50 mhz dram timing, 1-active ras mode. the 60/66 mhz ma [ 11:0 ] timings when in x-4-4-4 mode have one difference from the 82434LX ma [ 11:0 ] timings. the ma lines switch to the next address in the burst se- quence one clock sooner than in the 82434LX. the write cycle leadoffs are 1 clock earlier for 82430nx than 82430 (the migs and cas timings improved by 1 clock). the 0-active ras y modes closely resem- ble the row miss cases. in 0-active ras y mode, ras y is asserted one clock sooner than is shown in the row miss timing diagrams. 122
82434LX/82434nx 6.2.3.1 burst dram read page hit figure 55 depicts a cpu burst read page hit to dram. the 82434nx decodes the cpu address as a page hit and drives the column address onto the ma [ 11:0 ] lines. cas [ 7:0 ] y are then asserted for two clks and negated for one clk. cmr (cpu memory read) is driven on the hig [ 4:0 ] lines to en- able the memory data to host data path through the lbxs. the pcmc advances the ma [ 1:0 ] lines through the processor burst order, negating and as- serting cas [ 7:0 ] y to read each qword. the md [ 63:0 ] data is sampled with hclk in the lbxs when mdle is asserted, and driven on the host bus the following cycle to meet the setup time of the cpu. brdy y is then asserted. when mdle is neg- ated, the lbx continues to drive the latched hd [ 63:0 ] to ensure that the data hold time to cwe [ 7:0 ] y is met for standard srams. the lbxs tri-state the host data bus when hig [ 4:0 ] change to nopc and mdle rises. a single read page hit from dram is similar to the first read of this sequence. the hig [ 4:0 ] lines are driven to nopc when the last brdy y is asserted. the diagram also shows the typical control signal timing for a burst sram line fill operation. note that ccs y inactive will mask any new ads y (caused by the na y assertion) to the burst srams. 290479 64 figure 55. burst dram read cycle-page hit 123
82434LX/82434nx 6.2.3.2 burst dram read page miss figure 56 depicts a cpu to dram burst read page miss cycle. the 82434nx decodes the cpu address as a page miss and switches from initially driving the column address to driving the row address on the ma [ 11:0 ] lines. ras y is then negated to precharge the drams and then asserted to latch the new dram row address. the pcmc then switches the ma [ 11:0 ] lines to drive the column address and as- serts cas [ 7:0 ] y . cmr (cpu memory read) is driv- en on the hig [ 4:0 ] lines to enable the memory data to host data path through the lbxs. the pcmc ad- vances the ma [ 1:0 ] lines through the microproces- sor burst order, negating and asserting cas [ 7:0 ] y to read each qword. the md [ 63:0 ] data is sampled with hclk in the lbxs when mdle is asserted, and driven on the host bus the following cycle to meet the setup time of the cpu. brdy y is then asserted. when mdle is negated, the lbx continues to drive the latched hd [ 63:0 ] to ensure that the data hold time to cwe [ 7:0 ] y is met for standard srams. the lbxs tri-state the host data bus when hig [ 4:0 ] change to nopc and mdle rises. the hig [ 4:0 ] lines are driven to nopc when the last brdy y is asserted. 290479 65 figure 56. burst dram read cycle-page miss 124
82434LX/82434nx 6.2.3.3 burst dram read row miss figure 57 depicts a cpu to dram burst read row miss cycle. the 82434nx decodes the cpu address as a row miss and switches from initially driving the column address to driving the row address on the ma [ 11:0 ] lines. the ras y signal that was asserted is negated and the ras y for the currently accessed row is asserted (ras y is asserted 1 clock earlier in 0-active ras y mode.) the pcmc then switches the ma [ 11:0 ] lines to drive the column address and asserts cas [ 7:0 ] y . cmr (cpu memory read) is driven on the hig [ 4:0 ] lines to enable the memory data to host data path through the lbxs. the pcmc advances the ma [ 1:0 ] lines through the microproc- essor burst order, negating and asserting cas [ 7:0 ] y to read each qword. the md [ 63:0 ] data is sampled with hclk in the lbxs when mdle is asserted, and driven on the host bus the following cycle to meet the setup time of the cpu. brdy y is then asserted. when mdle is negated, the lbx continues to drive the latched hd [ 63:0 ] to ensure that the data hold time to cwe [ 7:0 ] y is met for standard srams. the lbxs tri-state the host data bus when hig [ 4:0 ] change to nopc and mdle ris- es. a single read row miss from dram is similar to the first read of this sequence. the hig [ 4:0 ] lines are driven to nopc when the last brdy y is asserted. 290479 66 figure 57. burst dram read cycle-row miss 125
82434LX/82434nx 6.2.3.4 burst dram write page hit figure 58 depicts a cpu burst write page hit to dram. the 82434nx decodes the cpu write cycle as a dram page hit. the hig [ 4:0 ] lines are driven to pcmwq to post the write to the lbxs. in the fig- ure, the write cycle is posted to the cpu-to-memory posted write buffer at 3-1-1-1. when the cycle is decoded as a page hit, the pcmc asserts we y and drives the rcmwq command on mig [ 2:0 ] to enable the lbxs to drive the first qword of the write onto the memory data lines. memdrv is then driven to cause the lbxs to continue to drive the first qword for two more clocks. cas [ 7:0 ] y are then negated and asserted to perform the writes to the drams as the ma [ 1:0 ] lines advance through the pentium processor burst order. a single write is similar to the first write of the burst sequence. the mig [ 2:0 ] lines are driven to nopm in the clock when the last cas [ 7:0 ] y are asserted. 290479 67 figure 58. burst dram write page miss 126
82434LX/82434nx 6.2.3.5 burst dram write page miss figure 59 depicts a cpu burst write page miss to dram. the 82434nx decodes the cpu write cycle as a dram page miss and drives the pcmwq com- mand [ hig [ 4:0 ] lines ] to post the write data to the lbxs. in the figure, the write cycle is posted to the cpu-to-memory posted write buffer at 3-1-1-1. when the cycle is decoded as a page miss, the pcmc switches the ma [ 11:0 ] lines from the column address to the row address and asserts we y in clock 4. the pcmc drives the rcmwq command on mig [ 2:0 ] to enable the lbxs to drive the first qword of the write onto the memory data lines. memdrv is then driven to cause the lbxs to con- tinue to drive the first qword. the ras y signal for the currently decoded row is negated to precharge the drams. ras y is then asserted to cause the drams to latch the row address. the pcmc then switches the ma [ 11:0 ] lines to the column address and asserts cas [ 7:0 ] y to initiate the first write. cas [ 7:0 ] y are then negated and asserted to per- form the writes to the drams as the ma [ 1:0 ] lines advance through the pentium processor burst order. a single write is similar to the first write of the burst sequence. the mig [ 2:0 ] lines are driven to nopm in the clock when the last cas [ 7:0 ] y are asserted. 290479 68 figure 59. burst dram write cycle-page miss 127
82434LX/82434nx 6.2.3.6 burst dram write row miss figure 60 depicts a cpu burst write row miss to dram. the 82434nx decodes the cpu write cycle as a dram row miss and the hig [ 4:0 ] lines are driv- en to pcmwq to post the write data into lbxs. when the cycle is decoded as a row miss, the pcmc negates the already active ras y signal, switches the ma [ 11:0 ] lines from the column address to the row address and asserts the ras y signal for the currently decoded row. the pcmc asserts we y and drives the rcmwq command on mig [ 2:0 ] to enable the lbxs to drive the first qword of the write onto the memory data lines. memdrv is then driven to cause the lbxs to continue to drive the first qword. the pcmc then switches the ma [ 11:0 ] lines to the column address and asserts cas [ 7:0 ] y to initiate the first write. cas [ 7:0 ] y are then negated and asserted to perform the writes to the drams as the ma [ 1:0 ] lines advance through the microproces- sor burst order. a single write is similar to the first write of the burst sequence. the mig [ 2:0 ] lines are driven to nopm in the clock when the last cas [ 7:0 ] y are asserted. 290479 69 figure 60. burst dram write cycle-row miss 128
82434LX/82434nx 6.2.4 refresh the refresh of the dram array can be performed by either using ras y -only or cas y -before-ras y refresh cycles. when programmed for cas y - before-ras y refresh, hidden refresh cycles are initiated when possible. the timing of internally gen- erated refresh cycles is derived from hclk and is independent of any expansion bus refresh cycles. the dram controller contains an internal refresh timer which periodically requests the refresh control logic to perform either a single refresh or a burst of four refreshes. the single refresh interval is 15.6 m s. the interval for burst of four refreshes is four times the single refresh interval, or 62.4 m s. the pcmc is configured for either single or burst of four refresh and either ras y -only or cas y -before ras y re- fresh via the dram control register (offset 57h). to minimize performance impact, refresh cycles are partially deferred until the dram interface is idle. refresh cycles are initiated such that the ras y maximum active time is never violated. hidden refresh cycles are run whenever all eight cas y lines are active at the end of a read transac- tion when the refresh cycle is internally requested. normal cas y -before-ras y refresh cycles are run whenever the dram interface is idle when the re- fresh is requested, or when any subset of the cas y lines is inactive as the refresh is internally requested. to minimize the power surge for refreshing a large dram array, the dram interface staggers the as- sertion and negation of the ras y signals during both cas y -before-ras y and ras y -only refresh cycles. the order of ras y edges is dependent on which ras y was most recently asserted prior to the refresh sequence. the ras y that was active will be the last to be activated during the refresh sequence. all ras [ 7:0 ] y lines are negated at the end of re- fresh cycles, making the first dram cycle after a refresh sequence a row miss. 6.2.4.1 ras y -only refreshesingle figure 61 depicts a ras y -only refresh cycle when the 82434nx is programmed for single refresh cy- cles. the diagram shows a cycle completing as the refresh timer inside the pcmc generates a refresh request. the refresh address is driven on the ma [ 11:0 ] lines. since the cycle was to row 0, ras0 y is negated. ras1 y is the first to be assert- ed. ras2 y through ras7 y are then asserted se- quentially while ras0 y is driven high, precharging the drams in row 0. ras0 y is then asserted after ras7 y . each ras y line is asserted for eight host clocks. 290479 70 figure 61. ras y -only refreshesingle 129
82434LX/82434nx 6.2.4.2 cas y -before-ras y refreshesingle figure 62 depicts a cas y -before-ras y refresh cycle when the 82434nx is programmed for single refresh cycles. the diagram shows a write cycle completing as the refresh timer inside the pcmc generates a refresh request. the cycle is less than a qword, therefore a hidden refresh is not initiated. after the cycle completes, all of the ras y and cas y lines are negated. the pcmc then asserts cas [ 7:0 ] y and then sequentially asserts the ras y lines, starting with ras1 y since ras0 y was the last ras y line asserted. each ras y line is assert- ed for eight clocks. 290479 71 figure 62. cas y -before-ras y refreshesingle 130
82434LX/82434nx 6.2.4.3 hidden refresh-single figure 63 depicts a hidden refresh cycle which takes place after a dram read page hit cycle. the dia- gram shows a read cycle completing as the refresh timing inside the 82434nx pcmc generates a re- fresh request. the cycle is an entire qword; there- fore, a hidden refresh is initiated. after the cycle completes, ras y is negated, but all eight cas y lines remain asserted. the pcmc then sequentially asserts the ras y lines, starting with ras1 y since ras0 y was the last active ras y line. each ras y line is asserted for eight clocks. 290479 72 figure 63. hidden refreshesingle 131
82434LX/82434nx 7.0 pci interface the description in this section applies to both the 82434LX and 82434nx. 7.1 pci interface overview the pcmc and lbxs form a high performance bridge from the pentium processor to pci and from pci to main memory. during pci-to-main memory cycles, the pcmc and lbxs act as a target on the pci bus, allowing pci masters to read from and write to main memory. during cpu cycles, the pcmc acts as a pci master. the cpu can then read and write i/o, memory and configuration spaces on pci. when the cpu accesses i/o mapped and con- figuration space mapped pcmc registers, the pcmc intercepts the cycles and does not forward them to pci. although these cpu cycles do not result in a pci bus cycle, they are described in this section since most of the pcmc internal registers are mapped into pci configuration space. 7.2 cpu-to-pci cycles 7.2.1 cpu write to pci figure 64 depicts a series of cpu memory writes which are posted to pci. the cpu initiates the cycles by asserting ads y and driving the memory address onto the host address lines. the pcmc asserts na y in the clock after ads y allowing the pentium processor to drive another cycle onto the host bus two clocks later. the pcmc decodes the memory address and drives pcpwl on the hig [ 4:0 ] lines, posting the host address bus and the low dword of the data bus to the lbxs. the pcmc as- serts brdy y , terminating the cpu cycle with one wait state. since na y is asserted in the second clock of the first cycle, the pentium processor does not insert an idle cycle after this cycle completes, but immediately drives the next cycle onto the bus. thus, the pentium processor maximum dword write bandwidth of 89 mbytes/second is achieved during back-to-back dword writes cycles. each of the fol- lowing write cycles is posted to the lbxs in three clocks. in this example, the pcmc is parked on pci and therefore, does not need to arbitrate for the bus. when parked, the pcmc drives the scpa command on the pig [ 3:0 ] lines and asserts drvpci, causing the host address lines to be driven on the pci ad [ 31:0 ] lines. after the write is posted, the pcmc drives the dcpwa command on the pig [ 3:0 ] lines to drive the previously posted address onto the ad [ 31:0 ] lines. the pcmc then drives dcpwd onto the pig [ 3:0 ] lines, to drive the previously posted write data onto the ad [ 31:0 ] lines. as this is occur- ring on pci, the second write cycle is being posted on the host bus. in this case, the second write is to a sequential and incrementing address. thus, the pcmc leaves frame y asserted, converting the write cycle into a pci burst cycle. the pcmc contin- ues to drive the dcpwd command on the pig [ 3:0 ] lines. the lbxs advance the posted write buffer pointer to point to the next posted dword when dcpwd is sampled on pig [ 3:0 ] and trdy y is sampled asserted. therefore, if the target inserts a wait-state by negating trdy y , the lbxs continue to drive the data for the current transfer. the remain- ing writes are posted on the host bus, while the pcmc and lbxs complete the writes on pci. cpu i/o write cycles to pci differ from the memory write cycle described here in that i/o writes are nev- er posted. brdy y is asserted to terminate the cycle only after trdy y is sampled asserted, completing the cycle on pci. 132
82434LX/82434nx 290479 73 figure 64. cpu memory writes to pci 7.3 register access cycles the pcmc contains two registers which are mapped into i/o space, the configuration space enable register (i/o port cf8h) and the turbo-reset con- trol register (i/o port cf9h). all other internal pcmc configuration registers are mapped into pci configuration space. configuration space must be enabled by writing a non-zero value to the key field in the cse register before accesses to these regis- ters can occur. these registers are mapped to loca- tions c000h through c0ffh in pci configuration space. if the key field is programmed with 0h, cpu i/o cycles to locations c000h through cfffh are forwarded to pci as ordinary i/o cycles. externally, accesses to the i/o mapped registers and the con- figuration space mapped registers use the same bus transfer protocol. only the pcmc internal decode of the cycle differs. na y is never asserted during pcmc configuration register or pci configuration register access cycles. see section 3.2, pci config- uration space mapped registers for details on the pcmc configuration space mapping mechanism. 133
82434LX/82434nx 7.3.1 cpu write cycle to pcmc internal register a write to an internal pcmc register (either cse register, trc register or a configuration space- mapped register) is shown in figure 65. the cycle begins with the address, byte enables and status signals (w/r y , d/c y and m/io y ) being driven to a valid state indicating an i/o write to either cf8h to access the cse register, cf9h to access the trc register or c0xxh when configuration space is en- abled to access a pcmc internal configuration regis- ter. the pcmc decodes the cycle and asserts ahold to tri-state the cpu address lines. the pcmc signals the lbxs to copy either the upper dword or the lower dword of the data bus onto the address lines. the pcmc makes the decision on which dword to copy based on the be [ 7:0 ] y lines. the hig [ 4:0 ] lines are driven to dacpyh or dacpyl depending on whether the lower dword of the data bus or the upper dword of the data bus needs to be copied onto the address bus. the lbxs sample the hig [ 4:0 ] command, and drive the data onto the address lines. the pcmc samples the a [ 31:0 ] lines on the second rising edge of hclk after the lbxs begin driving the data. finally, the pcmc negates ahold and asserts brdy y , termi- nating the cycle. if the write is to the cse register and the key field is programmed to 0000b then configuration space is disabled. if the key field is programmed to a non- zero value then configuration space is enabled. 290479 75 figure 65. cpu write to a pcmc configuration register 134
82434LX/82434nx 7.3.2 cpu read from pcmc internal register a read from an internal pcmc register (either cse register, trc register or a configuration space- mapped register) is shown in figure 66. the i/o read cycle is from either cf8h to access the cse register, cf9h to access the trc register or c0xxh when configuration space is enabled to access a configuration space-mapped register. the pcmc decodes the cycle and asserts ahold to tri-state the cpu address lines. the pcmc then drives the contents of the addressed register onto the a [ 31:0 ] lines. one byte is enabled on each rising hclk edge for four consecutive clocks. the pcmc signals the lbxs that the current cycle is a read from an internal pcmc register by issuing the adcpy command to the lbxs over the hig [ 4:0 ] lines. the lbxs sample the hig [ 4:0 ] command and copy the address lines onto the data lines. finally, the pcmc negates ahold, and asserts brdy y terminating the cycle. 290479 76 figure 66. cpu read from pcmc configuration register 135
82434LX/82434nx 7.3.3 cpu write to pci device configuration register in order to write to or read from a pci device config- uration register the key field in the cse register must be programmed to a non-zero value, enabling configuration space. when configuration space is enabled, pci device configuration registers are ac- cessed by cpu i/o accesses within the range of cnxxh where each pci device has a unique non- zero value of n. this allows a separate configuration space for each of 15 devices on pci. recall that when configuration space is enabled, the pcmc configuration registers are mapped into i/o ports c000h through c0ffh. a write to a pci device configuration register is shown in figure 67. the pcmc internally latches the host address lines and byte enables. the pcmc as- serts ahold to tri-state the cpu address bus and drives the address lines with the translated address for the pci configuration cycle. the translation is de- scribed in section 3.2, pci configuration space mapped registers. on the hig [ 4:0 ] lines, the pcmc signals the lbxs to latch either the upper dword of the host data bus or the lower dword of the host data bus to be driven onto pci during the data phase of the pci cycle. on the pig [ 3:0 ] lines, the pcmc signals the lbxs to drive the latched host address lines on the pci ad [ 31:0 ] lines. the upper two bytes of the address lines are used during configuration as idsel signals for the pci devices. the idsel pin on each pci device is connected to one of the ad [ 31:17 ] lines. the pcmc drives the command for a configuration write (1011) onto the c/be [ 3:0 ] y lines and asserts frame y for one pci clock. the pcmc drives the pig [ 3:0 ] lines signaling the lbxs to drive the con- tents of the pci write buffer onto the pci ad [ 31:0 ] lines. this command is driven for only one pci clock before returning to the scpa command on the pig [ 3:0 ] lines. the lbxs continue to drive the ad [ 31:0 ] lines with the valid write data as long as drvpci is asserted. the pcmc then asserts irdy y and waits until sampling the trdy y signal active. when trdy y is sampled asserted, the pcmc negates drvpci tri-stating the lbx ad [ 31:0 ] lines. brdy y is asserted for one clock to terminate the cpu cycle. 136
82434LX/82434nx 290479 77 figure 67. cpu write to pci device configuration register 137
82434LX/82434nx 7.3.4 cpu read from pci device configuration register in order to write to or read from a pci device config- uration register the key field in the cse register must be programmed to a non-zero value, enabling configuration space. when configuration space is enabled, pci device configuration registers are ac- cessed by cpu i/o accesses within the range of cnxxh where each pci device has a unique non- zero value of n. this allows a separate configuration space for each of 15 devices on pci. recall that when configuration space is enabled, the pcmc configuration registers occupy i/o addresses c0xxh. a cpu read from a pci device configuration register is shown in figure 68. the pcmc internally latches the host address lines and byte enables. the pcmc asserts ahold to tri-state the cpu address bus. the pcmc drives the address lines with the translat- ed address for the pci configuration cycle. the translation is described in section 3.2, pci configu- ration space mapped registers. on the pig [ 3:0 ] lines, the pcmc signals the lbxs to drive the latched host address lines on the pci ad [ 31:0 ] lines. the upper two bytes of the address lines are used during configuration as idsel signals for the pci devices. the idsel pin on each pci device is connected to one of the ad [ 31:17 ] lines. the pcmc drives the command for a configuration read (1010) onto the c/be [ 3:0 ] y lines and asserts frame y for one pci clock. the pcmc drives the pig [ 3:0 ] lines signaling the lbxs to latch the data on the pci ad [ 31:0 ] lines into the cpu-to-pci first read prefetch buffer. the pcmc then drives the hig [ 4:0 ] lines signaling the lbxs to drive the data from the buffer onto the host data lines. the pcmc asserts irdy y and waits until sampling trdy y ac- tive. after trdy y is sampled active, brdy y is as- serted for one clock to terminate the cpu cycle. 138
82434LX/82434nx 290479 78 figure 68. cpu read from pci device configuration register 139
82434LX/82434nx during system initialization, the cpu typically at- tempts to read from the configuration space of all 15 possible pci devices to detect the presence of the devices. if no device is present, devsel y is not be asserted and the cycle is terminated, returning ff . . . ffh to the cpu. figure 69 depicts an attempted read from a configuration register of a non-existent device. if no device responds then the pcmc aborts the cycle and sends the drvff com- mand over the hig [ 4:0 ] lines causing the lbxs to drive ff . . . ffh onto the host data lines. 290479 79 figure 69. cpu attempted configuration read from non-existent pci device 140
82434LX/82434nx 7.4 pci-to-main memory cycles 7.4.1 pci master write to main memory figure 70 depicts a pci master burst write to main memory. the pci master begins by driving the ad- dress on the ad [ 31:0 ] lines and asserting frame y . upon sampling frame y active, the pcmc drives the lcpa command on the pig [ 3:0 ] lines causing the lbxs to retain the address that was latched on the previous pclk rising edge. the pcmc then samples memcs y active, indicating that the cycle is directed to main memory. the pcmc drives the ppmwa command on the pig [ 3:0 ] lines to move the latched pci address into the write buffer address register. the pcmc then drives the dpwa com- mand on the hig [ 4:0 ] lines enabling the lbxs to drive the pci master write address onto the host address bus. the pcmc asserts eads y to initiate a first level cache snoop cycle and simultaneously be- gins an internal second level cache snoop cycle. since the snoop is a result of a pci master write, inv is asserted with eads y . hitm y remains nega- ted and the snoop either hits an unmodified line or misses in the second level cache, thus no write-back cycles are required. if the snoop hit an unmodified line in either the first or second level cache, the line is invalidated. the cycle is immediately forwarded to the dram interface. the four posted dwords are written to main memory as two qwords with two cas [ 7:0 ] y cycles. in this example, the dram inter- face is configured for x-3-3-3 write timing, thus each cas [ 7:0 ] y low pulse is two hclks in length. the pcmc disconnects the cycle by asserting stop y when one of the two four-dword-deep pci- to-memory posted write buffers is full. if the master terminates the cycle before sampling stop y as- serted, then irdy y , stop y and devsel y are negated when frame y is sampled negated. if the master intended to continue bursting, then the mas- ter negates frame y when it samples stop y as- serted. irdy y , stop y and devsel y are then negated one clock later. 141
82434LX/82434nx 290479 80 figure 70. pci master write to main memory-page hit 142
82434LX/82434nx 7.4.2 pci master read from main memory figure 71 depicts a pci master read from main memory. the pci master initiates the cycle by driv- ing the read address on the ad [ 31:0 ] lines and as- serting frame y . the pcmc drives the lpma com- mand on the pig [ 3:0 ] lines causing the lbxs to re- tain the address latched on the previous pclk rising edge. the pcmc drives the dpra command on the hig [ 4:0 ] lines enabling the lbxs to drive the read address onto the host address lines. the snoop cy- cle misses in the second level cache and either hits an unmodified line or misses in the first level cache. the cycle is then forwarded to the dram interface. a read of four qwords is performed. each qword is posted in the pci-memory read prefetch buffer. the data is then driven onto pci in an eight dword burst cycle. if the master terminates the cycle before sampling stop y , then irdy y , stop y and devsel y are all negated after frame y is sam- pled inactive. if the master intended to continue bursting, then the master negates frame y when it samples stop y asserted and irdy y , stop y and devsel y are negated one clock later. 290479 81 figure 71. pci master read from main memory-page hit 143
82434LX/82434nx 8.0 system clocking and reset 8.1 clock domains the 82434LX and 82434nx pcmcs and 82433lx and 82433nx lbxs operate based on two clocks, hclk and pclk. the cpu, second level cache, and the dram interfaces operate based on hclk. the pci interface timing is based on pclk. 8.2 clock generation and distribution figure 72 shows an example of the 82434LX and 82434nx pcmc host clock distribution in the cpu, cache and memory subsystem. hclk is distributed to the cpu, pcmc, lbxs and the second level cache srams (in the case of a burst sram second level cache). the host clock originates from an oscillator which is connected to the hclkosc input on the pcmc. the pcmc generates six low skew copies of hclk, hclka hclkf. figure 72 shows an example of a host clock distribution scheme for a uni-processor system. in this figure, clock loading is balanced with each hclk output driving two loads in the system. each clock output should drive a trace of length k with stubs at the end of the trace of length l connect- ing to the two loads. the l and k parameters should be matched for each of the six clock outputs to mini- mize overall system clock skew. one of the hclk outputs is used to clock the pcmc and the pentium processor. because the clock driven to the pcmc hclkin input and the pentium processor clk input originates with the same hclk output, clock skew between the pcmc and the cpu can be kept lower than between the pcmc and other system compo- nents. another copy of hclk is used to clock the lbxs. a 256 kbyte burst sram second level cache can be implemented with eight 32 kbyt e x 9 syn- chronous srams. the four remaining copies of hclk are used to clock the srams. each hclk output drives two srams. a 512 kbyte second level cache is implemented with four 64 kbyte x 18 syn- chronous srams. two of the four extra copies are used to clock the srams while the other two are unused. any one of the hclk outputs can be used to clock the pcmc and pentium processor, the two lbxs or any pair of srams. all six copies are identi- cal in drive strength. figure 73 depicts the pci clock distribution. 290479 82 figure 72. hclk distribution example 144
82434LX/82434nx 290479 83 figure 73. pci clock distribution the pcmc generates pclkout with an internal phase locked loop (pll). the pclkout signal is buffered using a single component to produce sev- eral low skew copies of pclk to drive the lbxs and other devices on pci. one of the outputs of the clock driver is directed back to the pclkin input on the pcmc. the pll locks the rising edges of pclkin in phase with the rising edges of hclkin. the pll effectively compensates for the delay of the external clock driver. the resulting pci clock is one half the frequency of hclk. timing for all of the pci interface signals is based on pclkin. all pci interface inputs are sampled on pclkin rising edg- es and all outputs transition as valid delays from pclkin rising edges. clock skew between the pclkin pin on the pcmc and the pclk pins on the lbxs must be kept within 1.25 ns to guarantee prop- er operation of the lbxs. 8.3 phase locked loop circuitry the 82434LX and 82434nx pcmcs each contain two internal phase locked loops (plls). loop fil- ters and power supply decoupling circuitry must be provided externally. figure 74 shows the pcmc con- nections to the external pll circuitry. one of the pcmc internal phase locked loops (pll) locks onto the hclkin input. the pll is used by the pcmc in generating and sampling timing crit- ical signals. an external loop filter is required. the pllarc1 and pllarc2 pins connect to the exter- nal hclk loop filter. two resistors and a capacitor form the loop filter. the loop filter circuitry should be placed as close as possible to the pcmc loop filter pins. the pll also has dedicated power and ground pins, pllavdd, pllavss and pllagnd. these power pins require a low noise supply. pllavdd, pllavss and pllagnd must be connected to the rc network shown in figure 74. the second pcmc internal phase locked loop (pll) locks the pclkin input in phase with the hclkin input. the pll is used by the pcmc to keep the pci clock in phase with the host clock. an external loop filter is required. the pllbrc1 and pllbrc2 pins connect to the external pclk loop filter. two resistors and a capacitor form the loop filter. the loop filter circuitry should be placed as close as possible to the pcmc loop filter pins. the pll also has dedicated power and ground pins, pllbvdd, pllbvss and pllbgnd. these power pins require a low noise supply. pllbvdd, pllbvss and pllbgnd must be connected to the rc network shown in figure 74. the resistance and capacitance values for the exter- nal pll circuitry are listed below. r1 e 10 k x g 5% r2 e 150 x g 5% r3 e 33 x g 5% c1 e 0.01 m f g 10% c2 e 0.47 m f g 10% an additional 0.01 m f capacitor in parallel with c2 will help to improve noise immunity. 145
82434LX/82434nx 290479 84 figure 74. pcmc pll circuitry connections 146
82434LX/82434nx 8.4 system reset figure 75 shows the 82434LX and 82434nx pcmc system reset connections. the 82434LX and 82434nx pcmc reset logic monitors pwrok and generates cpurst, pcirst y and init. when asserted, pwrok is an indicator to the pcmc that vdd and hclk have stabilized long enough for proper system operation. cpurst is asserted to ini- tiate hard reset. init is asserted to initiate soft reset. pcirst y is asserted to reset devices on pci. hard reset is initiated by the pcmc in response to one of two conditions. first, hard reset is initiated when power is first applied to the system. pwrok must be driven inactive and must not be asserted until 1 ms after vdd and hclk have stabilized at their ac and dc specifications. while pwrok is negated, the 82434LX asserts cpurst and pcirst y . pwrok can be asserted asynchronous- ly. when pwrok is asserted, the 82434LX first en- sures that it has been completely initialized before negating cpurst and pcirst y . cpurst is nega- ted synchronously to the rising edge of hclk. pcirst y is negated asynchronously. 290479 85 figure 75. pcmc system reset logic 147
82434LX/82434nx when pwrok is negated, the pcmc asserts ahold causing the cpu to tri-state the host ad- dress lines. address lines a [ 31:29 ] are sampled by the pcmc 1 ms after the rising edge of pwrok. the values sampled on a [ 31:30 ] are inverted inside the pcmc and then stored in configuration register 52h bits 7 and 6. the a [ 31:30 ] strapping options are depicted in table 18. table 18. a [ 31:30 ] strapping options configuration secondary a [ 31:30 ] register 52h, cache size bits [ 7:6 ] 11 00 not populated 10 01 reserved 01 10 256 kbyte cache 00 11 512 kbyte cache the value sampled on a29 is inverted inside the pcmc and stored in the sram type bit (bit 5) in the scc register. a28 is required to be pulled high for compatibility with future versions of the pcmc. the pcmc also initiates hard reset when the system hard reset enable bit in the turbo-reset control register (i/o address cf9h) is set to 1 and the re- set cpu bit toggles from 0 to 1. the pcmc drives cpurst and pcirst y active for a minimum of 1 ms. table 19 shows the state of all 82434LX pcmc output and bi-directional signals during hard reset. during hard reset both cpurst and pcirst y are asserted. when the hard reset is due to pwrok negation, ahold is asserted. the pcmc samples the strapping options on the a [ 31:29 ] lines 1 ms af- ter the rising edge of pwrok. when hard reset is initiated via a write to the turbo-reset control reg- ister (i/o port cf9h) ahold remains negated throughout the hard reset. table 19 also applies to the 82434nx, with the exception of the signals listed in section 8.5, 82434nx reset sequencing. table 19. 82434LX output and i/o signal states during hard reset signal state signal state a [ 31:0 ] input irdy y input ahold high/low ken y undefined boff y high ma [ 10:0 ] undefined brdy y high mdle high caa [ 6:3 ] undefined memack y high-z cab [ 6:3 ] undefined mig [ 2:0 ] low cads [ 1:0 ] y high na y high cadv [ 1:0 ] y high par input cale high pen y high cas [ 7:0 ] y high perr y input coe [ 1:0 ] y high plock y input cwe [ 7:0 ] y high pig3 low c/be [ 3:0 ] y input pig [ 2:0 ] high devsel y input ras [ 5:0 ] y high drvpci low req y high-z eads y high serr y input frame y input stop y input hig [ 4:0 ] low trdy y input init low we y high inv low soft reset is initiated by the pcmc in response to one of two conditions. first, when the system hard reset enable bit in the trc register is reset to 0, and the reset cpu bit toggles from 0 to 1, the pcmc initiates soft reset by asserting init for a min- imum of 2 hclks. second, the pcmc initiates a soft reset upon detecting a shutdown cycle from the cpu. in this case, the pcmc first broadcasts a shut- down special cycle on pci and then asserts init for a minimum of 2 hclks. 148
82434LX/82434nx 8.5 82434nx reset sequencing when pwrok is negated, the 82434nx pcmc drives the following signals lowebrdy y ,na y , ahold, eads y , inv, boff y , ken y , pen y , cpurst, init, cale, cads [ 1:0 ] y , cadv [ 1:0 ] y , caa [ 6:3 ] , cab [ 6:3 ] , coe [ 1:0 ] y , cwe [ 7:0 ] y . hclk [ a:f ] are driven as soon as the 3.3v supply is active. note that cwe [ 7:0 ] y low pre- vents the second level cache data rams from driv- ing the data bus, even though coe [ 1:0 ] y are also driven low. also, note that boff y driven low caus- es the cpu to tri-state all outputs to the 82434nx pcmc and 82433nx lbx, except hitm y , smiact y , and pchk y . this minimizes the number of signals that the cpu may drive to the pcmc when the 3.3v supply is active and the 5v supply is not active. figure 76 shows how the 82434nx sequences cpurst and pcirst y in response to pwrok as- sertion. some pci devices may drive 3.3v friendly signals directly to 3.3v devices that are not 5v tolerant. if such signals are powered from the 5v supply they must be driven low when pcirst y is asserted. some of these signals may need to be driven high before cpurst is negated. pcirst y is negated 1 ms before cpurst to allow time for this to occur. 290479 86 figure 76. 82434nx reset sequencing at power-up 149
82434LX/82434nx 9.0 electrical characteristics 9.1 absolute maximum ratings case temperature under bias 0 cto a 85 c storage temperature b 55 cto a 150 c voltage on any pin with respect to ground b 0.3 to v cc a 0.3v supply voltage with respect to v ss b 0.3 to a 6.5v maximum total power dissipation 2.0w maximum power dissipation, v cc 3 470 mw the maximum total power dissipation in the 82434nx on the v cc and v cc 3 pins is 2.0w. the v cc 3 pins may draw as much as 470 mw, however, total power will not exceed 2.0w. notice: this data sheet contains information on products in the sampling and initial production phases of development. the specifications are subject to change without notice. verify with your local intel sales office that you have the latest data sheet be- fore finalizing a design. * warning: stressing the device beyond the ``absolute maximum ratings'' may cause permanent damage. these are stress ratings only. operation beyond the ``operating conditions'' is not recommended and ex- tended exposure beyond the ``operating conditions'' may affect device reliability. 9.2 thermal characteristics the 82434LX and 82434nx pcmcs are designed for operation at case temperatures between 0 c and 85 c. the thermal resistances of the package are given in table 20. table 20. pcmc package thermal resistance parameter air flow meters/second (linear feet per minute) 0 0.5 1.0 2.0 5.0 (0) (98.4) (196.9) (393.7) (984.3) i ja ( c/watt) 31 27 24.5 23 19 i jc ( c/watt) 8.6 9.3 82434LX dc characteristics functional operating range (v cc e 5v g 5%; t case e 0 cto a 85 c) symbol parameter min max unit test conditions v il1 input low voltage b 0.3 0.8 v note 1, v cc e 4.75v v ih1 input high voltage 2.2 v cc a 0.3 v note 1, v cc e 5.25v v il2 input low voltage b 0.3 1.35 v note 2, v cc e 4.75v v ih2 input high voltage 3.85 v cc a 0.3 v note 2, v cc e 5.25v v t1 schmitt trigger threshold voltage, 0.7 1.35 v note 3, v cc e 5.0v falling edge v t1 a schmitt trigger threshold voltage, 1.4 2.2 v note 3, v cc e 5.0v falling edge v h1 hysteresis voltage 0.3 1.2 v note 3, v cc e 5.0v v t2 b schmitt trigger threshold voltage, 1.25 2.3 v note 3, v cc e 5.0v falling edge v t2 a schmitt trigger threshold voltage, 2.3 3.7 v note 3, v cc e 5.0v rising edge v h2 hysterersis voltage 0.3 1.2 v note 3, v cc e 5.0v 150
82434LX/82434nx functional operating range (v cc e 5v g 5%; t case e 0 cto a 85 c) (continued) symbol parameter min max unit test conditions v ol1 output low voltage 0.5 v note 4 v oh1 output high voltage v cc b 0.5 v note 4 v ol2 output low voltage 0.4 v note 5 v oh2 output high voltage 2.4 v note 5 i ol1 output low current 1 ma note 6 i oh1 output high current b 1 ma note 6 i ol2 output low current 3 ma note 7 i oh2 output high current b 2 ma note 7 i ol3 output low current 6 ma note 8 i oh3 output high current b 2 ma note 8 i ol4 output low current 3 ma note 9 i oh4 output high current b 1 ma note 9 i ih input leakage current a 10 ua i il input leakage current b 10 ua c in input capacitance 12 pf f c e 1 mhz c out output capacitance 12 pf f c e 1 mhz c i/o i/o capacitance 12 pf f c e 1 mhz notes: 1. v il1 and v ih1 apply to the following signals: a [ 31:0 ] ,be [ 7:0 ] y , d/c y , w/r y , m/io y , hlock y , ads y , pchk y , hitm y , cache y , smiact y , pclkin, hclkin, hclkosc, flshbuf y , memcs y , serr y , perr y , memreq y , gnt y , plock y , stop y , irdy y , trdy y , frame y , c/be [ 3:0 ] y . 2. v il2 and v ih2 apply to the following signals: ppout [ 1:0 ] , eol. 3. v t1 b ,v t1 a and v h1 apply to pwrok. v t2 b ,v t2 a and v h2 apply to testen. 4. v ol1 and v oh1 apply to the following signals: hig [ 4:0 ] , mig [ 2:0 ] , pig [ 3:0 ] , drvpci, mdle, pcirst y . 5. v ol2 and v oh2 apply to the following signals: req y , memack y , frame y , c/be [ 3:0 ] y , trdy y , irdy y , stop y , plock y , devsel y , par, perr y , serr y , boff y , ahold, brdy y ,na y , eads y , ken y , inv, a [ 31:0 ] , pclkout, hclka hclkf, cale, coe [ 1:0 ] y , cwe [ 7:0 ] y , cadv [ 1:0 ] y , cads [ 1:0 ] y , caa [ 6:3 ] , cab [ 6:3 ] , ras [ 5:0 ] y , cas [ 7:0 ] y ,ma [ 10:0 ] ,we y . 6. i ol1 and i oh1 apply to the following signals: hig [ 4:0 ] , mig [ 2:0 ] , pig [ 3:0 ] , drvpci, mdle, pcirst y . 7. i ol2 and i oh2 apply to the following signals: c/be [ 3:0 ] y , req y , memack y ,ma [ 10:0 ] ,we y . 8. i ol3 and i oh3 apply to the following signals: frame y , trdy y , irdy y , stop y , plock y , devsel y , par, perr y , serr y . 9. i ol4 and i oh4 apply to the following signals: boff y , ahold, brdy y ,na y , eads y , ken y , inv, cpurst, init, a [ 31:0 ] , pclkout, cale, coe [ 1:0 ] y , cads [ 1:0 ] y , cadv [ 1:0 ] y , cwe [ 7:0 ] y , caa [ 6:3 ] , cab [ 6:3 ] , ras [ 5:0 ] y , cas [ 7:0 ] y . 151
82434LX/82434nx 9.4 82434nx dc characteristics functional operating range (v cc e 5v g 5%; v cc 3 e 3.135 to 3.465 v; t case e 0 cto a 85 c) symbol parameter min max unit test conditions v il1 input low voltage b 0.3 0.8 v note 1, v cc e 4.75v v ih1 input high voltage 2.2 v cc a 0.3 v note 1, v cc e 5.25v v il2 input low voltage b 0.3 1.35 v note 2, v cc e 4.75v v ih2 input high voltage 3.85 v cc a 0.3 v note 2, v cc e 5.25v v il3 input low voltage b 0.3 0.8 v note 3, v ccq e 3.135v v ih3 input high voltage 2.2 v cc a 0.3 v note 3, v ccq e 3.465v v t1 schmitt trigger threshold voltage, falling edge 0.7 1.35 v note 4, v cc e 5.0v v t1 a schmitt trigger threshold voltage, rising edge 1.4 2.2 v note 4, v cc e 5.0v v h1 hysteresis voltage 0.3 1.2 v note 4, v cc e 5.0v v t2 b schmitt trigger threshold voltage, falling edge 1.25 2.3 v note 4, v cc e 5.0v v t2 a schmitt trigger threshold voltage, rising edge 2.3 3.7 v note 4, v cc e 5.0v v h2 hysterersis voltage 0.3 1.2 v note 4, v cc e 5.0v v ol1 output low voltage 0.5 v note 5 v oh1 output high voltage v cc b 0.5 v note 5 v ol2 output low voltage 0.4 v note 6 v oh2 output high voltage 2.4 v note 6 i ol1 output low current 1 ma note 7 i oh1 output high current b 1 ma note 7 i ol2 output low current 3 ma note 8 152
82434LX/82434nx functional operating range (v cc e 5v g 5%; v cc 3 e 3.135 to 3.465 v; t case e 0 cto a 85 c) (continued) symbol parameter min max unit test conditions i oh2 output high current b 2 ma note 8 i ol3 output low current 6 ma note 9 i oh3 output high current b 2 ma note 9 i ol4 output low current 3 ma note 10 i oh4 output high current b 1 ma note 10 i ih input leakage current a 10 ua i il input leakage current b 10 ua c in input capacitance 12 pf f c e 1 mhz c out output capacitance 12 pf f c e 1 mhz c i/o i/o capacitance 12 pf f c e 1 mhz notes: 1. v il1 and v ih1 apply to the following signals: be [ 7:0 ] y , d/c y , w/r y , m/io y , hlock y , ads y , pchk y , hitm y , cache y , smiact y , pclkin, hclkosc, flshbuf y , memcs y , serr y , perr y , memreq y , gnt y , plock y , stop y , irdy y , trdy y , frame y , c/be [ 3:0 ] y . 2. v il2 and v ih2 apply to the following signals: ppout [ 1:0 ] , eol. 3. vil3 and vih3 apply to the following signals: a [ 31:0 ] , hclkin. 4. v t1 b ,v t1 a and v h1 apply to pwrok. v t2 b ,v t2 a and v h2 apply to testen. 5. v ol1 and v oh1 apply to the following signals: hig [ 4:0 ] , mig [ 2:0 ] , pig [ 3:0 ] , drvpci, mdle, pcirst y . 6. v ol2 and v oh2 apply to the following signals: req y , memack y , frame y , c/be [ 3:0 ] y , trdy y , irdy y , stop y , plock y , devsel y , par, perr y , serr y , boff y , ahold, brdy y ,na y , eads y , ken y , inv, a [ 31:0 ] , pclkout, hclka hclkf, cale, coe [ 1:0 ] y , cwe [ 7:0 ] y , cadv [ 1:0 ] y , cads [ 1:0 ] y , caa [ 6:3 ] , cab [ 6:3 ] , ras [ 7:0 ] y , cas [ 7:0 ] y ,ma [ 11:0 ] ,we y . 7. i ol1 and i oh1 apply to the following signals: hig [ 4:0 ] , mig [ 2:0 ] , pig [ 3:0 ] , drvpci, mdle, a [ 31:8 ] ,a [ 2:0 ] , pcirst y . 8. i ol2 and i oh2 apply to the following signals: c/be [ 3:0 ] y , req y , memack y ,ma [ 11:0 ] ,we y . 9. i ol3 and i oh3 apply to the following signals: frame y , trdy y , irdy y , stop y , plock y , devsel y , par, perr y , serr y . 10. i ol4 and i oh4 apply to the following signals: boff y , ahold, brdy y ,na y , eads y , ken y , inv, cpurst, init, a [ 7:3 ] , pclkout, cale, coe [ 1:0 ] y , cads [ 1:0 ] y , cadv [ 1:0 ] y , cwe [ 7:0 ] y , caa [ 6:3 ] , cab [ 6:3 ] , ras [ 7:0 ] y , cas [ 7:0 ] y . 11. the output buffers for brdy y ,na y , ahold, eads y , inv, boff y , ken y , pen y , cpurst, init, cale, cads [ 1:0 ] , cadv [ 1:0 ] y , caa [ 6:3 ] , cab [ 6:3 ] , coe [ 1:0 ] y , cwe [ 7:0 ] y ,a [ 31:3 ] and hclk [ a:f ] are powered with v cc 3 and there- fore drive 3.3v signal levels. 153
82434LX/82434nx 9.5 82434LX ac characteristics the ac characteristics given in this section consist of propagation delays, valid delays, input setup require- ments, input hold requirements, output float delays, output enable delays, output-to-output delays, pulse widths, clock high and low times and clock period specifications. figure 77 through figure 85 define these specifications. section 9.5 lists the 82434LX ac characteristics. output test loads are listed in the right column. in figure 77 through figure 85, vt e 1.5v for the following signals: a [ 31:0 ] ,be [ 7:0 ] y , pen y , d/c y , w/r y , m/io y , hlock y , ads y , pchk y , hitm y , eads y , brdy y , boff y , ahold, na y , ken y , inv, cache y , smiact y , init, cpurst, cale, cadv [ 1:0 ] y , coe [ 1:0 ] y , cwe [ 7:0 ] y , cads [ 1:0 ] y , caa [ 6:3 ] , cab [ 6:3 ] ,we y , ras [ 5:0 ] y , cas [ 7:0 ] y ,ma [ 10:0 ] , c/be [ 3:0 ] y , frame y , trdy y , irdy y , stop y , plock y , gnt y , devsel y , memreq y , par, perr y , serr y , req y , memcs y , flshbuf y ,memack y , pwrok, hclkin, hclka hclkf, pclkin, pclkout. vt e 2.5v for the following signals: ppout [ 1:0 ] , eol, hig [ 4:0 ] , pig [ 3:0 ] , mig [ 2:0 ] , drvpci, mdle, pcirst y . 9.5.1 host clock timing, 66 mhz (82434LX) functional operating range (v cc e 4.9v to 5.25v; t case e 0 cto a 70 c) symbol parameter min max figure notes t1a hclkosc high time 6.0 82 t1b hclkosc low time 5.0 82 t2a hclkin period 15 20 82 t2b hclkin period stability g 100 ps (1) t2c hclkin high time 4 82 t2d hclkin low time 4 82 t2e hclkin rise time 1.5 83 t2f hclkin fall time 1.5 83 t3a hclka hclkf output-to-output skew 0.5 85 0 pf t3b hclka hclkf high time 5.0 85 0 pf t3c hclka hclkf low time 5.0 85 0 pf note: 1. measured on rising edge of adjacent clocks at 1.5v. 154
82434LX/82434nx 9.5.2 cpu interface timing, 66 mhz (82434LX) functional operating range (v cc e 4.9v to 5.25v; t case e 0 cto a 70 c) symbol parameter min max fig notes t10a ads y , hitm y , w/r y , m/io y , d/c y , 4.6 79 hlock y , cache y ,be [ 7:0 ] y , smiact y setup time to hclkin rising t10b ads y , hitm y , w/r y , m/io y , d/c y , 0.8 79 hlock y , cache y ,be [ 7:0 ] y , smiact y hold time from hclkin rising t11a pchk y setup time to hclkin rising 4.3 79 t11b pchk y hold time from hclkin rising 1.1 79 t12a a [ 18:3 ] rising edge setup time to 4.5 79 setup to hclkin rising when hclkin rising ads y is sampled active by pcmc. t12aa a [ 18:3 ] falling edge setup time to 3.2 79 setup to hclkin rising when hclkin rising ads y is sampled active by pcmc. t12ab a [ 18:3 ] rising edge setup time to 4.7 setup to hclkin rising when hclkin rising ads y is sampled active by pcmc. t12ac a [ 18:3 ] falling edge setup time to 4.1 setup to hclkin rising when hclkin rising ads y is sampled active by pcmc. t12b a [ 31:0 ] hold time from hclkin rising 0.5 79 hold from hclkin rising two clocks after ads y is sampled active by pcmc. t12c a [ 31:0 ] setup time to hclkin rising 6.5 79 setup to hclkin rising when eads y is sampled active by the cpu. t12d a [ 31:0 ] hold time from hclkin rising 1.5 79 hold from hclkin rising when eads y is sampled active by the cpu. 155
82434LX/82434nx functional operating range (v cc e 4.9v to 5.25v; t case e 0 cto a 70 c) (continued) symbol parameter min max fig notes t12e a [ 31:0 ] output enable from hclkin 0 13 81 rising t12f a [ 31:0 ] valid delay from hclkin 1.3 13 78 0 pf rising t12g a [ 31:0 ] float delay from hclkin 0 13 80 rising t12h a [ 2:0 ] propagation delay from 1 16 77 0 pf be [ 7:0 ] y t13a brdy y rising edge valid delay 1.7 7.8 78 0 pf from hclkin rising t13b brdy y falling edge valid delay 1.7 7.6 78 0 pf from hclkin rising t14 na y valid delay from hclkin 1.3 7.8 78 0 pf rising t15a ahold valid delay from hclkin 1.3 7.1 78 0 pf rising t15b boff y valid delay from hclkin 1.8 7.1 78 rising t16a eads y , inv, pen y valid delay from 1.3 7.4 78 0 pf hclkin rising t16b cpurst rising edge valid delay 0.9 7.5 78 from hclkin rising t16c cpurst falling edge valid delay 0.9 7.0 78 from hclkin rising t16d ken y valid delay from hclkin 1.3 7.6 78 rising t17 init high pulse width 2 hclks 84 soft reset via trc register or cpu shutdown special cycle t18 cpurst high pulse width 1 ms 84 hard reset via trc register, 0 pf 156
82434LX/82434nx 9.5.3 second level cache standard sram timing, 66 mhz (82434LX) functional operating range (v cc e 4.9v to 5.25v; t case e 0 cto a 70 c) symbol parameter min max fig notes t20a caa [ 6:3 ] /cab [ 6:3 ] propagation 0 8.5 77 0 pf delay from a [ 6:3 ] t20b caa [ 6:3 ] /cab [ 6:3 ] valid delay from 0 7.2 78 0 pf hclkin rising t21a coe [ 1:0 ] y falling edge valid delay 0 9 78 0 pf from hclkin rising t21b coe [ 1:0 ] y rising edge valid delay 0 5.5 78 0 pf from hclkin rising t22a cwe [ 7:0 ] y /cbs [ 7:0 ] y falling edge 2 14 78 cpu burst or single write to valid delay from hclkin rising second level cache, 0 pf t22b cwe [ 7:0 ] y /cbs [ 7:0 ] y rising edge 3 14 78 cpu burst or single write to valid delay from hclkin rising second level cache, 0 pf t22c cwe [ 7:0 ] y /cbs [ 7:0 ] y valid delay 1.4 7.7 78 cache line fill, 0 pf from hclkin rising t22d cwe [ 7:0 ] y /cbs [ 7:0 ] y low pulse 1 hclk 84 0 pf width t22e cwe [ 7:0 ] y /cbs [ 7:0 ] y driven high -1 85 last write to second level cache before cale driven high during cache line fill, 0 pf t22f caa [ 4:3 ] /cab [ 4:3 ] valid before 1.5 85 cpu burst write to second level cwe [ 7:0 ] y falling cache, 0 pf t23 cale valid delay from hclkin 0 7.5 78 0 pf rising t24 cr/w [ 1:0 ] y valid delay from 1.5 7.6 78 0 pf hclkin rising t25 cbs [ 1:0 ] y valid delay from hclkin 1.0 12.0 78 0 pf rising; reads from cache srams 157
82434LX/82434nx 9.5.4 second level cache burst sram timing, 66 mhz (82434LX) functional operating range (v cc e 4.9v to 5.25v; t case e 0 cto a 70 c) symbol parameter min max fig notes t30a caa [ 6:3 ] /cab [ 6:3 ] propagation delay from a [ 6:3 ] 0 8.5 77 0 pf t30b caa [ 6:3 ] /cab [ 6:3 ] valid delay from hclkin rising 0 7.0 78 0 pf t31 cads [ 1:0 ] y valid delay from hclkin rising 1.5 7.7 78 0 pf t32 cadv [ 1:0 ] y valid delay from hclkin rising 1.5 7.1 78 0 pf t33 cwe [ 7:0 ] y valid delay from hclkin rising 1.0 9.0 78 0 pf t34a coe [ 1:0 ] y falling edge valid delay from hclkin rising 0 9.0 78 0 pf t34b coe [ 1:0 ] y rising edge valid delay from hclkin rising 0 5.5 78 0 pf t35 cale valid delay from hclkin rising 0 7.5 78 0 pf 9.5.5 dram interface timing, 66 mhz (82434LX) functional operating range (v cc e 4.9v to 5.25v; t case e 0 cto a 70 c) symbol parameter min max fig notes t40a ras [ 5:0 ] y valid delay from 0 7.5 78 50 pf hclkin rising t40b ras [ 5:0 ] y pulse width high 4 hclks b 5 84 ras y precharge at beginning of page miss cycle, 50 pf t41a cas [ 7:0 ] y valid delay from 0 7.5 78 50 pf hclkin rising t41b cas [ 7:0 ] y pulse width high 1 hclkin b 5 84 cas y precharge during burst cycles, 50 pf t42 we y valid delay from hclkin 0 21 78 50 pf rising t43a ma [ 10:0 ] propagation delay from 0 23 77 50 pf a [ 23:3 ] t43b ma [ 10:0 ] valid delay from 0 10.1 78 50 pf hclkin rising 9.5.6 pci clock timing, 66 mhz (82434LX) functional operating range (v cc e 4.9v to 5.25v; t case e 0 cto a 70 c) symbol parameter min max fig notes t50a pclkout high time 13 82 20 pf t50b pclkout low time 13 82 20 pf t51a pclkin high time 12 82 t51b pclkin low time 12 82 t51c pclkin rise time 3 83 t51d pclkin fall time 3 83 158
82434LX/82434nx 9.5.7 pci interface timing, 66 mhz (82434LX) functional operating range (v cc e 4.9v to 5.25v; t case e 0 cto a 70 c) symbol parameter min max fig notes t60a c/be [ 3:0 ] y , frame y , trdy y , irdy y , stop y , 2 11 78 min: 0 pf plock y , par, perr y , serr y , devsel y valid max: 50 pf delay from pclkin rising t60b c/be [ 3:0 ] y , frame y , trdy y , irdy y , stop y ,2 81 plock y , par, perr y , serr y , devsel y output enable delay from pclkin rising t60c c/be [ 3:0 ] y , frame y , trdy y , irdy y , stop y , 2 28 80 plock y , par, perr y , serr y , devsel y float delay from pclkin rising t60d c/be [ 3:0 ] y , frame y , plock y , par, perr y ,7 79 serr y , setup time to pclkin rising t60da trdy y , irdy y setup time to pclkin rising 8.1 77 t60db stop y , devsel y setup time to pclkin rising 8.5 77 t60e c/be [ 3:0 ] y , frame y , plock y , par, perr y ,0 77 serr y hold time from pclkin rising t61a req y , memack y valid delay from pclkin rising 2 12 78 min: 0 pf max: 50 pf t61b req y , memack y output enable delay from 2 81 pclkin rising t61c req y , memack y float delay from pclkin rising 2 28 80 t62a flshreq y , memreq y setup time to pclkin 12 79 rising t62b flshreq y , memreq y hold time from pclkin 0 79 rising t63a gnt y setup time to pclkin rising 10 79 t63b gnt y hold time from pclkin rising 0 79 t64a memcs y setup time to pclkin rising 7 79 t64b memcs y hold time from pclkin rising 0 79 t65 pcirst y low pulse width 1 ms 84 hard reset via trc register, 0 pf 159
82434LX/82434nx 9.5.8 lbx interface timing, 66 mhz (82434LX) functional operating range (v cc e 4.9v to 5.25v; t case e 0 cto a 70 c) symbol parameter min max fig notes t70 hig [ 4:0 ] valid delay from hclkin rising 0.8 6.5 78 0 pf t71 mig [ 2:0 ] valid delay from hclkin rising 0.9 6.5 78 0 pf t72 pig [ 3:0 ] valid delay from pclkin rising 0.7 10.9 78 0 pf t73 pcidrv valid delay from pclkin rising 1 13.5 78 0 pf t74a mdle falling edge valid delay from hclkin rising 0.6 5.6 78 0 pf t74b mdle rising edge valid delay from hclkin rising 0.6 6.8 85 0 pf t75a eol, ppout [ 1:0 ] setup time to pclkin rising 7.7 79 t75b eol, ppout [ 1:0 ] hold time from pclkin rising 1.0 79 9.5.9 host clock timing, 60 mhz (82434LX) functional operating range (v cc e 4.75v to 5.25v; t case e 0 cto a 85 c) symbol parameter min max fig notes t1a hclkosc high time 6.0 82 t1b hclkosc low time 5.0 82 t2a hclkin period 16.66 20 82 t2b hclkin period stability g 100 ps (1) t2c hclkin high time 4 82 t2d hclkin low time 4 82 t2e hclkin rise time 1.5 83 t2f hclkin fall time 1.5 83 t3a hclka hclkf output-to-output skew 0.5 85 0 pf t3b hclka hclkf high time 5.0 82 0 pf t3c hclka hclkf low time 5.0 82 0 pf note: 1. measured on rising edge of adjacent clocks at 1.5v. 160
82434LX/82434nx 9.5.10 cpu interface timing, 60 mhz (82434LX) functional operating range (v cc e 4.75v to 5.25v; t case e 0 cto a 85 c) symbol parameter min max fig notes t10a ads y , hitm y , w/r y , m/io y , d/c y , 4.6 79 hlock y , cache y ,be [ 7:0 ] y , smiact y setup time to hclkin rising t10b ads y , hitm y , w/r y , m/io y , d/c y , 1.1 79 hlock y , cache y ,be [ 7:0 ] y , smiact y hold time from hclkin rising t11a pchk y setup time to hclkin rising 4.3 79 t11b pchk y hold time from hclkin rising 1.1 79 t12a a [ 18:3 ] rising edge setup time to 4.5 79 setup to hclkin rising when hclkin rising ads y is sampled active by pcmc. t12aa a [ 18:3 ] falling edge setup time to 3.2 79 setup to hclkin rising when hclkin rising ads y is sampled active by pcmc. t12ab a [ 18:3 ] rising edge setup time to 4.7 79 setup to hclkin rising when hclkin rising ads y is sampled active by pcmc. t12ac a [ 18:3 ] falling edge setup time to 4.1 79 setup to hclkin rising when hclkin rising ads y is sampled active by pcmc. t12b a [ 31:0 ] hold time from hclkin rising 0.5 79 hold from hclkin rising two clocks after ads y is sampled active by pcmc. t12c a [ 31:0 ] setup time to hclkin rising 6.5 79 setup to hclkin rising when eads y is sampled active by the cpu. t12d a [ 31:0 ] hold time from hclkin rising 1.5 79 hold from hclkin rising when eads y is sampled active by the cpu. t12e a [ 31:0 ] output enable from hclkin 0 13 81 rising t12f a [ 31:0 ] valid delay from hclkin rising 1.3 13 78 0 pf t12g a [ 31:0 ] float delay from hclkin 0 13 80 rising 161
82434LX/82434nx functional operating range (v cc e 4.75v to 5.25v; t case e 0 cto a 85 c) (continued) symbol parameter min max fig notes t12h a [ 2:0 ] propagation delay from 1 16 77 0 pf be [ 7:0 ] y t13a brdy y rising edge valid delay 2.1 7.9 78 0 pf from hclkin rising t13b brdy y falling edge valid delay 2.1 7.9 78 0 pf from hclkin rising t14 na y valid delay from hclkin 1.4 8.4 78 0 pf rising t15a ahold valid delay from hclkin 2.0 7.6 78 0 pf rising t15b boff y valid delay from hclkin 2.0 7.6 78 rising t16a eads y , inv, pen y valid delay from 2.0 8.0 78 0 pf hclkin rising t16b cpurst rising edge valid delay 1.2 7.5 78 from hclkin rising t16c cpurst falling edge valid delay 1.2 7.5 78 from hclkin rising t16d ken y valid delay from hclkin 1.7 8.2 78 rising t17 init high pulse width 2 hclks 84 soft reset via trc register or cpu shutdown special cycle t18 cpurst high pulse width 1 ms 84 hard reset via trc register, 0 pf 162
82434LX/82434nx 9.5.11 second level cache standard sram timing, 60 mhz (82434LX) functional operating range (v cc e 4.75v to 5.25v; t case e 0 cto a 85 c) symbol parameter min max fig notes t20a caa [ 6:3 ] /cab [ 6:3 ] 0 8.5 77 0 pf propagation delay from a [ 6:3 ] t20b caa [ 6:3 ] /cab [ 6:3 ] valid 0 7.2 78 0 pf delay from hclkin rising t21a coe [ 1:0 ] y falling edge valid 0 9 78 0 pf delay from hclkin rising t21b coe [ 1:0 ] y rising edge valid 0 5.5 78 0 pf delay from hclkin rising t22a cwe [ 7:0 ] y /cbs [ 7:0 ] y 2 14 78 cpu burst or single write to second falling edge valid delay from level cache, 0 pf hclkin rising t22b cwe [ 7:0 ] y /cbs [ 7:0 ] y rising 3 15 78 cpu burst or single write to second edge valid delay from hclkin level cache, 0 pf rising t22c cwe [ 7:0 ] y /cbs [ 7:0 ] y valid 1.4 7.7 78 cache line fill, 0 pf delay from hclkin rising t22d cwe [ 7:0 ] y /cbs [ 7:0 ] y low 1 hclk 84 0 pf pulse width t22e cwe [ 7:0 ] y /cbs [ 7:0 ] y driven b 1 85 last write to second level cache during high before cale driven high cache line fill, 0 pf t22f caa [ 4:3 ] /cab [ 4:3 ] valid 1.5 85 cpu burst write to second level cache, before cwe [ 7:0 ] y falling 0 pf t23 cale valid delay from hclkin 0 8 78 0 pf rising t24 cr/w [ 1:0 ] y valid delay from 1.5 8.2 78 0 pf hclkin rising t25 cbs [ 1:0 ] y valid delay from 1.0 12.0 78 0 pf hclkin rising; reads from cache srams 163
82434LX/82434nx 9.5.12 second level cache burst sram timing, 60 mhz (82434LX) functional operating range (v cc e 4.75v to 5.25v; t case e 0 cto a 85 c) symbol parameter min max fig notes t30a caa [ 6:3 ] /cab [ 6:3 ] propagation delay from a [ 6:3 ] 0 8.5 77 0 pf t30b caa [ 6:3 ] /cab [ 6:3 ] valid delay from hclkin rising 0 8.2 78 0 pf t31 cads [ 1:0 ] y valid delay from hclkin rising 1.5 8.2 78 0 pf t32 cadv [ 1:0 ] y valid delay from hclkin rising 1.5 8.2 78 0 pf t33 cwe [ 7:0 ] y valid delay from hclkin rising 1.0 10.5 78 0 pf t34a coe [ 1:0 ] y falling edge valid delay from hclkin rising 0 9.5 78 0 pf t34b coe [ 1:0 ] y rising edge valid delay from hclkin rising 0 6.0 78 0 pf t35 cale valid delay from hclkin rising 0 8.5 78 0 pf 9.5.13 dram interface timing, 60 mhz (82434LX) functional operating range (v cc e 4.75v to 5.25v; t case e 0 cto a 85 c) symbol parameter min max fig notes t40a ras [ 5:0 ] y valid delay from 0 8.0 78 50 pf hclkin rising t40b ras [ 5:0 ] y pulse width high 4 hclks b 5 84 ras y precharge at beginning of page miss cycle, 50 pf t41a cas [ 7:0 ] y valid delay from 0 8.0 78 50 pf hclkin rising t41b cas [ 7:0 ] y pulse width high 1 hclk b 5 84 cas y precharge during burst cycles, 50 pf t42 we y valid delay from hclkin 0 21 78 50 pf rising t43a ma [ 10:0 ] propagation delay from 0 23 77 50 pf a [ 23:3 ] t43b ma [ 10:0 ] valid delay from hclkin 0 10.7 78 50 pf rising 164
82434LX/82434nx 9.5.14 pci clock timing, 60 mhz (82434LX) functional operating range (v cc e 4.75v to 5.25v; t case e 0 cto a 85 c) symbol parameter min max fig notes t50a pclkout high time 13 82 20 pf t50b pclkout low time 13 82 20 pf t51a pclkin high time 12 82 t51b pclkin low time 12 82 t51c pclkin rise time 3 83 t51d pclkin fall time 3 83 9.5.15 pci interface timing, 60 mhz (82434LX) functional operating range (v cc e 4.75v to 5.25v; t case e 0 cto a 85 c) symbol parameter min max fig notes t60a c/be [ 3:0 ] y , frame y , trdy y , irdy y , stop y , plock y , 2 11 78 min: 0 pf par, perr y , serr y , devsel y valid delay from pclkin max: 50 pf rising t60b c/be [ 3:0 ] y , frame y , trdy y , irdy y , stop y , plock y ,2 81 par, perr y , serr y , devsel y output enable delay from pclkin rising t60c c/be [ 3:0 ] y , frame y , trdy y , irdy y , stop y , plock y , 2 28 80 par, perr y , serr y , devsel y float delay from pclkin rising t60d c/be [ 3:0 ] y , frame y , trdy y , irdy y , stop y , plock y ,9 79 par, perr y , serr y , devsel y setup time to pclkin rising t60e c/be [ 3:0 ] y , frame y , trdy y , irdy y , stop y , plock y ,0 79 par, perr y , serr y , devsel y hold time from pclkin rising t61a req y , memack y valid delay from pclkin rising 2 12 78 min: 0 pf max: 50 pf t61b req y , memack y output enable delay from pclkin rising 2 81 t61c req y , memack y float delay from pclkin rising 2 28 80 t62a flshreq y , memreq y setup time to pclkin rising 12 79 165
82434LX/82434nx functional operating range (v cc e 4.75v to 5.25v; t case e 0 cto a 85 c) (continued) symbol parameter min max fig notes t62b flshreq y , memreq y hold time 0 79 from pclkin rising t63a gnt y setup time to pclkin rising 10 79 t63b gnt y hold time from pclkin rising 0 79 t64a memcs y setup time to pclkin rising 7 79 t64b memcs y hold time from pclkin rising 0 79 t65 pcirst y low pulse width 1 ms 84 hard reset via trc register, 0pf 9.5.16 lbx interface timing, 60 mhz (82434LX) functional operating range (v cc e 4.75v to 5.25v; t case e 0 cto a 85 c) symbol parameter min max fig notes t70 hig [ 4:0 ] valid delay from hclkin rising 0.8 6.7 78 0 pf t71 mig [ 2:0 ] valid delay from hclkin rising 0.9 6.5 78 0 pf t72 pig [ 3:0 ] valid delay from pclkin rising 1.5 12 78 0 pf t73 pcidrv valid delay from pclkin rising 1 13 78 0 pf t74a mdle falling edge valid delay from hclkin rising 0.6 6.8 78 0 pf t74b mdle rising edge valid delay from hclkin rising 0.6 6.8 85 0 pf t75a eol, ppout [ 1:0 ] setup time to pclkin rising 7.7 79 t75b eol, ppout [ 1:0 ] hold time from pclkin rising 1.0 79 166
82434LX/82434nx 9.6 82434nx ac characteristics the ac characteristics given in this section consist of propagation delays, valid delays, input setup require- ments, input hold requirements, output float delays, output enable delays, output-to-output delays, pulse widths, clock high and low times and clock period specifications. figure 77 through figure 85 define these specifications. output test loads are listed in the right column. in figure 77 through figure 85, vt e 1.5v for the following signals: a [ 31:0 ] ,be [ 7:0 ] y , pen y , d/c y , w/r y , m/io y , hlock y , ads y , pchk y , hitm y , eads y , brdy y , boff y , ahold, na y , ken y , inv, cache y , smiact y , init, cpurst, cale, cadv [ 1:0 ] y , coe [ 1:0 ] y , cwe [ 7:0 ] y , cads [ 1:0 ] y , caa [ 6:3 ] , cab [ 6:3 ] ,we y , ras [ 5:0 ] y , cas [ 7:0 ] y ,ma [ 10:0 ] , c/be [ 3:0 ] y , frame y , trdy y , irdy y , stop y , plock y , gnt y , devsel y , memreq y , par, perr y , serr y , req y , memcs y , flshbuf y , memack y , pwrok, hclkin, hclka hclkf, pclkin, pclkout. vt e 2.5v for the following signals: ppout [ 1:0 ] , eol, hig [ 4:0 ] , pig [ 3:0 ] , mig [ 2:0 ] , drvpci, mdle, pcirst y 9.6.1 host clock timing, 66 mhz (82434nx), preliminary functional operating range (v cc e 4.75v to 5.25v; v cc 3 e 3.135v to 3.465v; t case e 0 cto a 85 c) symbol parameter min max fig notes t1a hclkosc high time 6.0 82 t1b hclkosc low time 5.0 82 t2a hclkin period 15 20 82 t2b hclkin period stability g 100 ps (1) t2c hclkin high time 4 82 t2d hclkin low time 4 82 t2e hclkin rise time 1.5 83 t2f hclkin fall time 1.5 83 t3a hclka hclkf output-to-output skew 0.5 85 0 pf t3b hclka hclkf high time 5.0 82 0 pf t3c hclka hclkf low time 5.0 82 0 pf notes: 1. measured on rising edge of adjacent clocks at 1.5v. 167
82434LX/82434nx 9.6.2 cpu interface timing, 66 mhz (82434nx), preliminary functional operating range (v cc e 4.75v to 5.25v; v cc 3 e 3.135v to 3.465v; t case e 0 cto a 85 c) symbol parameter min max fig notes t10a ads y , w/r y , setup time to hclkin 4.6 79 rising t10b be [ 7:0 ] y setup time to hclkin rising 4.6 79 t10c hitm y setup time to hclkin rising 6.4 79 t10d cache y , m/io y setup time to 4.6 79 hclkin rising t10e d/c y setup time to hclkin rising 4.0 79 t10f hlock y , smiact y , setup time to 4.0 79 hclkin rising t10g hitm y , m/io y , d/c y , hold time from 0.7 79 hclkin rising t10h w/r y , hlock y , hold time from 0.8 79 hclkin rising t10i ads y ,be [ 7:0 ] y hold time from 1.1 79 hclkin rising t10j cache y , smiact y hold time from 1.1 79 hclkin rising t11a pchk y setup time to hclkin rising 4.3 79 t11b pchk y hold time from hclkin rising 1.1 79 t12a a [ 31:0 ] setup time to hclkin rising 2.7 79 setup to hclkin rising when ads y is sampled active by pcmc. t12b a [ 31:0 ] hold time from hclkin rising 0.5 hold from hclkin rising two clocks after ads y is sampled active by pcmc t12c a [ 31:0 ] setup time to hclkin rising 6.0 79 setup to hclkin rising when eads y is sampled active by the cpu. 168
82434LX/82434nx functional operating range (v cc e 4.75v to 5.25v; v cc 3 e 3.135v to 3.465v; t case e 0 cto a 85 c) (continued) symbol parameter min max fig notes t12d a [ 31:0 ] hold time from hclkin 1.5 79 hold from hclkin rising when rising eads y is sampled active by the cpu. t12e a [ 31:0 ] output enable from hclkin 0 13 81 rising t12f a [ 31:0 ] valid delay from hclkin 1.3 13 78 0 pf rising t12g a [ 31:0 ] float delay from hclkin 0 13 80 rising t12h a [ 2:0 ] propagation delay from 1.0 16 77 0 pf be [ 7:0 ] y t13a brdy y rising edge valid delay 1.6 7.5 78 0 pf from hclkin rising t13b brdy y falling edge valid delay 1.6 7.5 78 0 pf from hclkin rising t14 na y valid delay from hclkin .9 7.6 78 0 pf rising t15a ahold valid delay from hclkin 1.5 7.0 78 0 pf rising t15b boff y valid delay from hclkin 1.5 7.0 78 0 pf rising t16a eads y , inv, pen y valid delay from 1.5 7.5 78 0 pf hclkin rising t16b cpurst rising edge valid delay 1.2 7.0 78 0 pf from hclkin rising t16c cpurst falling edge valid delay 1.2 7.0 78 0 pf from hclkin rising t16d ken y valid delay from hclkin 1.5 7.5 78 0 pf rising t17 init high pulse width 2 hclks 84 0 pf t18 cpurst high pulse width 1 ms 84 0 pf; hard reset via trc register 169
82434LX/82434nx 9.6.3 second level cache standard sram timing, 66 mhz (82434nx), preliminary functional operating range (v cc e 4.75v to 5.25v; v cc 3 e 3.135v to 3.465v; t case e 0 cto a 85 c) symbol parameter min max fig notes t20a caa [ 6:3 ] /cab [ 6:3 ] propagation delay from 0 8.5 77 0 pf a [ 6:3 ] t20b caa [ 6:3 ] /cab [ 6:3 ] valid delay from 0 7.2 78 0 pf hclkin rising t21a coe [ 1:0 ] y falling edge valid delay from 0 9 78 0 pf hclkin rising t21b coe [ 1:0 ] y rising edge valid delay from 0 5.5 78 0 pf hclkin rising t22a cwe [ 7:0 ] y /cbs [ 7:0 ] y falling edge valid 2 14 78 cpu burst or single write to delay from hclkin rising second level cache, 0 pf t22b cwe [ 7:0 ] y /cbs [ 7:0 ] y rising edge valid 3 14 78 cpu burst or single write to delay from hclkin rising second level cache, 0 pf t22c cwe [ 7:0 ] y /cbs [ 7:0 ] y valid delay from 1.0 7.7 78 cache line fill, 0 pf hclkin rising t22d cwe [ 7:0 ] y /cbs [ 7:0 ] y low pulse width 1 hclk 84 0 pf t22e cwe [ 7:0 ] y /cbs [ 7:0 ] y driven high before b 1 85 last write to second level cale driven high cache during cache line fill, 0 pf t22f caa [ 4:3 ] /cab [ 4:3 ] valid before 1.5 85 cpu burst write to second cwe [ 7:0 ] y falling level cache, 0 pf t23 cale valid delay from hclkin rising 0 8.0 78 0 pf t24 cr/w [ 1:0 ] y valid delay from hclkin 1.5 8.2 78 0 pf rising t25 cbs [ 1:0 ] y valid delay from hclkin 1.0 12.0 78 0 pf rising; reads from cache srams t26a ccs [ 1:0 ] y propagation delay from ads y 7.0 77 0 pf; first access falling after powerdown t26b ccs [ 1:0 ] y valid delay from hclkin rising 1.5 8.2 78 0 pf; entering powerdown 170
82434LX/82434nx 9.6.4 second level cache burst sram timing, 66 mhz (82434nx), preliminary functional operating range (v cc e 4.75v to 5.25v; v cc 3 e 3.135v to 3.465v; t case e 0 cto a 85 c) symbol parameter min max fig notes t30a caa [ 6:3 ] /cab [ 6:3 ] propagation delay from a [ 6:3 ] 0 8.5 77 0 pf t30b caa [ 6:3 ] /cab [ 6:3 ] valid delay from hclkin rising 0 8.2 78 0 pf t31 cads [ 1:0 ] y valid delay from hclkin rising 1.5 8.0 78 0 pf t32 cadv [ 1:0 ] y valid delay from hclkin rising 1.5 8.0 78 0 pf t33 cwe [ 7:0 ] y valid delay from hclkin rising 1.5 9.0 78 0 pf t34a coe [ 1:0 ] y falling edge valid delay from hclkin rising 0.5 9.0 78 0 pf t34b coe [ 1:0 ] y rising edge valid delay from hclkin rising 0.5 6.0 78 0 pf t35 cale valid delay from hclkin rising 0 8.0 78 0 pf 9.6.5 dram interface timing, 66 mhz (82434nx), preliminary functional operating range (v cc e 4.75v to 5.25v; v cc 3 e 3.135v to 3.465v; t case e 0 cto a 85 c) symbol parameter min max fig notes t40a ras [ 7:0 ] y valid delay from 0 8.0 78 50 pf hclkin rising t40b ras [ 7:0 ] y pulse width high 4 hclks b 5 84 ras y precharge at beginning of page miss cycle, 50 pf t41a cas [ 7:0 ] y valid delay from 0 8.0 78 50 pf hclkin rising t41b cas [ 7:0 ] y pulse width high 1 hclkin b 5 84 cas y precharge during burst cycles, 50 pf t42 we y valid delay from hclkin 0 21 78 50 pf rising t43a ma [ 10:0 ] propagation delay from 0 23 77 50 pf a [ 23:3 ] t43b ma [ 10:0 ] valid delay from hclkin 0 10.7 78 50 pf rising t43c ma11 propagation delay from 0 28.0 77 50 pf a [ 25:24 ] t43d ma11 valid delay from hclkin 0 12 78 50 pf rising 171
82434LX/82434nx 9.6.6 pci clock timing, 66 mhz (82434nx), preliminary functional operating range (v cc e 4.75v to 5.25v; v cc 3 e 3.135v to 3.465v; t case e 0 cto a 85 c) symbol parameter min max fig notes t50a pclkout high time 13 82 20 pf t50b pclkout low time 13 82 20 pf t51a pclkin high time 12 82 t51b pclkin low time 12 82 t51c pclkin rise time 3 83 t51d pclkin fall time 3 83 9.6.7 pci interface timing, 66 mhz (82434nx), preliminary functional operating range (v cc e 4.75v to 5.25v; v cc 3 e 3.135v to 3.465v; t case e 0 cto a 85 c) symbol parameter min max fig notes t60a c/be [ 3:0 ] y , frame y , trdy y , irdy y , stop y , plock y , 2 11 78 min: 0 pf par, perr y , serr y , devsel y valid delay from pclkin max: 50 pf rising t60b c/be [ 3:0 ] y , frame y , trdy y , irdy y , stop y , plock y ,2 81 par, perr y , serr y , devsel y output enable delay from pclkin rising t60c c/be [ 3:0 ] y , frame y , trdy y , irdy y , stop y , plock y , 2 28 80 par, perr y , serr y , devsel y float delay from pclkin rising t60d c/be [ 3:0 ] y , frame y , trdy y , irdy y , stop y , plock y ,7 79 par, perr y , serr y , devsel y setup time to pclkin rising t60e c/be [ 3:0 ] y , frame y , trdy y , irdy y , stop y , plock y ,0 79 par, perr y , serr y , devsel y hold time from pclkin rising t61a req y , memack y valid delay from pclkin rising 2 12 78 min: 0 pf max: 50 pf t61b req y , memack y output enable delay from pclkin rising 2 81 t61c req y , memack y float delay from pclkin rising 2 28 80 t62a flshreq y , memreq y setup time to pclkin rising 12 79 t62b flshreq y , memreq y hold time from pclkin rising 0 79 172
82434LX/82434nx functional operating range (v cc e 4.75v to 5.25v; v cc 3 e 3.135v to 3.465v; t case e 0 cto a 85 c) (continued) symbol parameter min max fig notes t63a gnt y setup time to pclkin rising 10 79 t63b gnt y hold time from pclkin rising 0 79 t64a memcs y setup time to pclkin rising 7 79 t64b memcs y hold time from pclkin rising 0 79 t65 pcirst y low pulse width 1 ms 84 hard reset via trc register,0 pf 9.6.8 lbx interface timing, 66 mhz (82434nx), preliminary functional operating range (v cc e 4.75v to 5.25v; v cc 3 e 3.135v to 3.465v; t case e 0 cto a 85 c) symbol parameter min max fig notes t70 hig [ 4:0 ] valid delay from hclkin rising 0.8 6.5 78 0 pf t71 mig [ 2:0 ] valid delay from hclkin rising 0.9 6.5 78 0 pf t72 pig [ 3:0 ] valid delay from pclkin rising 1.5 12 78 0 pf t73 pcidrv valid delay from pclkin rising 1 13 78 0 pf t74a mdle falling edge valid delay from hclkin rising 0.6 6.0 78 0 pf t74b mdle rising edge valid from hclkin rising 0.6 6.0 85 0 pf t75a eol, ppout [ 1:0 ] setup time to pclkin rising 7.7 79 t75b eol, ppout [ 1:0 ] hold time from pclkin rising 1.0 79 9.6.9 host clock timing, 50 and 60 mhz (82434nx) functional operating range (v cc e 4.75v to 5.25v; v cc 3 e 3.135v to 3.465v; t case e 0 cto a 85 c) symbol parameter min max fig notes t1a hclkosc high time 6.0 82 t1b hclkosc low time 5.0 82 t2a hclkin period 16.66 20 82 t2b hclkin period stability g 100 ps (1) t2c hclkin high time 4 82 t2d hclkin low time 4 82 t2e hclkin rise time 1.5 83 t2f hclkin fall time 1.5 83 t3a hclka hclkf output-to-output skew 0.5 85 0 pf t3b hclka hclkf high time 5.0 82 0 pf t3c hclka hclkf low time 5.0 82 0 pf notes: 1. measured on rising edge of adjacent clocks at 1.5v. 173
82434LX/82434nx 9.6.10 cpu interface timing, 50 and 60 mhz (82434nx) functional operating range (v cc e 4.75v to 5.25v; v cc 3 e 3.135v to 3.465v; t case e 0 cto a 85 c) symbol parameter min max fig notes t10a ads y , w/r y , setup time to hclkin 4.6 79 rising t10b be [ 7:0 ] y setup time to hclkin rising 4.6 79 t10c hitm y setup time to hclkin rising 6.8 79 t10d cache y , m/io y setup time to 4.6 79 hclkin rising t10e d/c y setup time to hclkin rising 4.6 79 t10f hlock y , smiact y , setup time to 4.6 79 hclkin rising t10g hitm y , m/io y , d/c y , hold time from 0.7 79 hclkin rising t10h w/r y , hlock y hold from hclkin 0.8 79 rising t10i ads y ,be [ 7:0 ] y hold time from 0.9 79 hclkin rising t10j cache y , smiact y hold time from 1.1 79 hclkin rising t11a pchk y setup time to hclkin rising 4.3 79 t11b pchk y hold time from hclkin rising 1.1 79 t12a a [ 31:0 ] setup time to hclkin rising 3.0 79 setup to hclkin rising when ads y is sampled active by pcmc. t12b a [ 31:0 ] hold time from hclkin rising 0.5 79 hold from hclkin rising two clocks after ads y is sampled active by pcmc t12c a [ 31:0 ] setup time to hclkin rising 6.5 79 setup to hclkin rising when eads y is sampled active by the cpu. t12d a [ 31:0 ] hold time from hclkin rising 1.5 79 hold from hclkin rising when eads y is sampled active by the cpu. 174
82434LX/82434nx functional operating range (v cc e 4.75v to 5.25v; v cc 3 e 3.135v to 3.465v; t case e 0 cto a 85 c) (continued) symbol parameter min max fig notes t12e a [ 31:0 ] output enable from hclkin 0 13 81 rising t12f a [ 31:0 ] valid delay from hclkin 1.3 13 78 0 pf rising t12g a [ 31:0 ] float delay from hclkin 0 13 80 rising t12h a [ 2:0 ] propagation delay from 1.0 16 77 0 pf be [ 7:0 ] y t13a brdy y rising edge valid delay 2.1 7.9 78 0 pf from hclkin rising t13b brdy y falling edge valid delay 2.1 7.9 78 0 pf from hclkin rising t14 na y valid delay from hclkin 1.4 8.4 78 0 pf rising t15a ahold valid delay from hclkin 2.0 7.6 78 0 pf rising t15b boff y valid delay from hclkin 2.0 7.6 78 0 pf rising t16a eads y , inv, pen y valid delay from 2.0 8.0 78 0 pf hclkin rising t16b cpurst rising edge valid delay 1.2 7.5 78 0 pf from hclkin rising t16c cpurst falling edge valid delay 1.2 7.5 78 0 pf from hclkin rising t16d ken y valid delay from hclkin 1.7 8.2 78 0 pf rising t17 init high pulse width 2 hclks 84 0 pf t18 cpurst high pulse width 1 ms 84 0 pf; hard reset via trc register 175
82434LX/82434nx 9.6.11 second level cache standard sram timing, 50 and 60 mhz (82434nx) functional operating range (v cc e 4.75v to 5.25v; v cc 3 e 3.135v to 3.465v; t case e 0 cto a 85 c) symbol parameter min max fig notes t20a caa [ 6:3 ] /cab [ 6:3 ] propagation delay 0 8.5 77 0 pf from a [ 6:3 ] t20b caa [ 6:3 ] /cab [ 6:3 ] valid delay from 0 7.2 78 0 pf hclkin rising t21a coe [ 1:0 ] y falling edge valid delay 0 9.0 78 0 pf from hclkin rising t21b coe [ 1:0 ] y rising edge valid delay 0 5.5 78 0 pf from hclkin rising t22a cwe [ 7:0 ] y /cbs [ 7:0 ] y falling edge 2 14 78 second level cache, 0 pf cpu burst or single write to valid delay from hclkin rising t22b cwe [ 7:0 ] y /cbs [ 7:0 ] y rising edge 3 15 78 second level cache, 0 pf cpu burst or single write to valid delay from hclkin rising t22c cwe [ 7:0 ] y /cbs [ 7:0 ] y valid delay 1.4 7.7 78 cache line fill, 0 pf from hclkin rising t22d cwe [ 7:0 ] y /cbs [ 7:0 ] y low pulse 14 84 0 pf width t22e cwe [ 7:0 ] y /cbs [ 7:0 ] y driven high -1 85 cache during cache line fill, 0 pf last write to second level before cale driven high t22f caa [ 4:3 ] /cab [ 4:3 ] valid before 1.5 85 second level cache, 0 pf cpu burst write to cwe [ 7:0 ] y falling t23 cale valid delay from hclkin rising 0 8 78 0 pf t24 cr/w [ 1:0 ] y valid delay from hclkin 1.5 8.2 78 0 pf rising t25 cbs [ 1:0 ] y valid delay from hclkin 1.0 12.0 78 0 pf rising; reads from cache srams t26a ccs [ 1:0 ] y propagation delay from 7.0 77 powerdown 0 pf; first access after ads y falling t26b ccs [ 1:0 ] y valid delay from hclkin 1.5 8.2 78 0 pf; entering powerdown rising 176
82434LX/82434nx 9.6.12 second level cache burst sram timing, 50 and 60 mhz (82434nx) functional operating range (v cc e 4.75v to 5.25v; v cc 3 e 3.135v to 3.465v; t case e 0 cto a 85 c) symbol parameter min max fig notes t30a caa [ 6:3 ] /cab [ 6:3 ] propagation delay from a [ 6:3 ] 0 8.5 77 0 pf t30b caa [ 6:3 ] /cab [ 6:3 ] valid delay from hclkin rising 0 8.2 78 0 pf t31 cads [ 1:0 ] y valid delay from hclkin rising 1.5 8.2 78 0 pf t32 cadv [ 1:0 ] y valid delay from hclkin rising 1.5 8.2 78 0 pf t33 cwe [ 7:0 ] y valid delay from hclkin rising 1.0 10.5 78 0 pf t34a coe [ 1:0 ] y falling edge valid delay from hclkin rising 0 9.5 78 0 pf t34b coe [ 1:0 ] y rising edge valid delay from hclkin rising 0 6.0 78 0 pf t35 cale valid delay from hclkin rising 0 8.5 78 0 pf 9.6.13 dram interface timing, 50 and 60 mhz (82434nx) functional operating range (v cc e 4.75v to 5.25v; v cc 3 e 3.135v to 3.465v; t case e 0 cto a 85 c) symbol parameter min max fig notes t40a ras [ 7:0 ] y valid delay from 0 8.0 78 50 pf hclkin rising t40b ras [ 7:0 ] y pulse width high 4 hclks 5 84 ras y precharge at beginning of page miss cycle, 50 pf t41a cas [ 7:0 ] y valid delay from 0 8.0 78 50 pf hclkin rising t41b cas [ 7:0 ] y pulse width high 1 hclk 5 84 cas y precharge during burst cycles, 50 pf t42 we y valid delay from hclkin 0 21 78 50 pf rising t43a ma [ 10:0 ] propagation delay from 0 23 77 50 pf a [ 23:3 ] t43b ma [ 10:0 ] valid delay from hclkin 0 10.7 78 50 pf rising t43c ma11 propagation delay from 0 24.3 77 50 pf a [ 25:24 ] t43d ma11 valid delay from hclkin 0 12 78 50 pf rising 177
82434LX/82434nx 9.6.14 pci clock timing, 50 and 60 mhz (82434nx) functional operating range (v cc e 4.75v to 5.25v; v cc 3 e 3.135v to 3.465v; t case e 0 cto a 85 c) symbol parameter min max fig notes t50a pclkout high time 13 82 20 pf t50b pclkout low time 13 82 20 pf t51a pclkin high time 12 82 t51b pclkin low time 12 82 t51c pclkin rise time 3 83 t51d pclkin fall time 3 83 9.6.15 pci interface timing, 50 and 60 mhz (82434nx) functional operating range (v cc e 4.75v to 5.25v; v cc 3 e 3.135v to 3.465v; t case e 0 cto a 85 c) symbol parameter min max fig notes t60a c/be [ 3:0 ] y , frame y , trdy y , irdy y , stop y , plock y , 2 11 78 min: 0 pf par, perr y , serr y , devsel y valid delay from pclkin max: 50 pf rising t60b c/be [ 3:0 ] y , frame y , trdy y , irdy y , stop y , plock y ,2 81 par, perr y , serr y , devsel y output enable delay from pclkin rising t60c c/be [ 3:0 ] y , frame y , trdy y , irdy y , stop y , plock y , 2 28 80 par, perr y , serr y , devsel y float delay from pclkin rising t60d c/be [ 3:0 ] y , frame y , trdy y , irdy y , stop y , plock y ,9 79 par, perr y , serr y , devsel y setup time to pclkin rising t60e c/be [ 3:0 ] y , frame y , trdy y , irdy y , stop y , plock y ,0 79 par, perr y , serr y , devsel y hold time from pclkin rising t61a req y , memack y valid delay from pclkin rising 2 12 78 min: 0 pf max: 50 pf t61b req y , memack y output enable delay from pclkin rising 2 81 t61c req y , memack y float delay from pclkin rising 2 28 80 t62a flshreq y , memreq y setup time to pclkin rising 12 79 t62b flshreq y , memreq y hold time from pclkin rising 0 79 t63a gnt y setup time to pclkin rising 10 79 t63b gnt y hold time from pclkin rising 0 79 t64a memcs y setup time to pclkin rising 7 79 t64b memcs y hold time from pclkin rising 0 79 t65 pcirst y low pulse width 1 ms 84 hard reset via trc register, 0pf 178
82434LX/82434nx 9.6.16 lbx interface timing, 50 and 60 mhz (82434nx) functional operating range (v cc e 4.75v to 5.25v; v cc 3 e 3.135v to 3.465v; t case e 0 cto a 85 c) symbol parameter min max fig notes t70 hig [ 4:0 ] valid delay from hclkin rising 0.8 6.7 78 0 pf t71 mig [ 2:0 ] valid delay from hclkin rising 0.9 6.5 78 0 pf t72 pig [ 3:0 ] valid delay from pclkin rising 1.5 12 78 0 pf t73 pcidrv valid delay from pclkin rising 1 13 78 0 pf t74a mdle falling edge valid delay from hclkin rising 0.6 6.8 78 0 pf t74b mdle rising edge valid delay from hclkin rising 0.6 6.8 85 0 pf t75a eol, ppout [ 1:0 ] setup time to pclkin rising 7.7 79 t75b eol, ppout [ 1:0 ] hold time from pclkin rising 1.0 79 9.6.17 timing diagrams 290479 87 figure 77. propagation delay 290479 88 figure 78. valid delay from rising clock edge 290479 89 figure 79. setup and hold times 179
82434LX/82434nx 290479 90 figure 80. float delay 290479 91 figure 81. output enable delay 290479 92 figure 82. clock high and low times and period 290479 93 figure 83. clock rise and fall times 180
82434LX/82434nx 290479 94 figure 84. pulse width 290479 95 figure 85. output-to-output delay 181
82434LX/82434nx 10.0 pinout and package information 10.1 pin assignment except for the pins listed in figure 86 notes, the pin assignment for the 82434LX and 82434nx are the same. 290479 96 notes: 1. for the 82434nx, pin 105 e ras6 y , 106 e ras7 y , and 109 e ma11. these pins are no connects for the 82434LX and are signal connections for the 82434nx. 2. for the 82434nx, pins 23, 35, 43, 74, 86, and 102 are 3.3v vdd pins (i.e., vdd3). these pins are vdd pins for the 82434LX. figure 86. pcmc pin assignment 182
82434LX/82434nx table 21. 82434LX alphabetical pin assignment pin name pin y type a0 204 t/s a1 205 t/s a2 206 t/s a3 12 t/s a4 9 t/s a5 10 t/s a6 11 t/s a7 14 t/s a8 13 t/s a9 16 t/s a10 15 t/s a11 18 t/s a12 17 t/s a13 19 t/s a14 21 t/s a15 22 t/s a16 201 t/s a17 202 t/s a18 203 t/s a19 6 t/s a20 7 t/s a21 200 t/s a22 4 t/s a23 196 t/s a24 3 t/s a25 8 t/s a26 5 t/s a27 197 t/s a28 2 t/s a29 198 t/s a30 207 t/s a31 199 t/s ads y 66 in pin name pin y type ahold 33 out be0 y 56 in be1 y 53 in be2 y 57 in be3 y 59 in be4 y 55 in be5 y 54 in be6 y 58 in be7 y 60 in boff y 30 out brdy y 32 out caa3 82 out caa4 80 out caa5 78 out caa6 76 out cab3 84 out cab4 81 out cab5 79 out cab6 77 out cache y 64 in cads0 y ,cr/w0 y 93 out cads1 y ,cr/w1 y 94 out cadv0 y (82434LX) 88 out cadv0 y /ccs0 y (82434nx) cadv1 y (82434LX) 89 out cadv1 y /ccs1 y (82434nx) cale 101 out cas0 y 135 out cas1 y 137 out cas2 y 133 out cas3 y 131 out cas4 y 136 out pin name pin y type cas5 y 138 out cas6 y 134 out cas7 y 132 out cbe0 y 146 t/s cbe1 y 145 t/s cbe2 y 144 t/s cbe3 y 143 t/s coe0 y 87 out coe1 y 85 out cpurst 25 out cwe0 y /cbs0 y 100 out cwe1 y /cbs1 y 99 out cwe2 y /cbs2 y 98 out cwe3 y /cbs3 y 97 out cwe4 y /cbs4 y 96 out cwe5 y /cbs5 y 95 out cwe6 y /cbs6 y 91 out cwe7 y /cbs7 y 90 out d/c y 68 in devsel y 170 s/t/s drvpci 186 out eads y 34 out eol 161 in flshreq y 162 in frame y 173 s/t/s gnt y 163 in hclka 42 out hclkb 41 out hclkc 40 out hclkd 39 out hclke 38 out hclkf 37 out hclkin 50 in 183
82434LX/82434nx table 21. 82434LX alphabetical pin assignment (continued) pin name pin y type hclkosc 52 in hig0 184 out hig1 183 out hig2 182 out hig3 181 out hig4 180 out hitm y 65 in hlock y 71 in init 26 out inv 28 out irdy y 142 s/t/s ken y 29 out m/io y 61 in ma0 122 out ma1 121 out ma2 119 out ma3 118 out ma4 117 out ma5 116 out ma6 114 out ma7 113 out ma8 112 out ma9 111 out ma10 110 out pin name pin y type ma11 109 out (82434nx only) mdle 185 out memack y 195 out memcs y 164 in memreq y 165 in mig0 179 out mig1 178 out mig2 175 out na y 31 out nc 70 nc nc (82434LX only) 105 nc nc (82434LX only) 106 nc nc (82434LX only) 109 nc par 171 t/s pchk y 72 in pcirst y 147 out pclkin 156 in pclkout 174 out pen y 27 out perr y 169 s/o/d pig0 193 out pig1 192 out pig2 191 out pig3 187 out pin name pin y type pllagnd 45 v pllarc1 46 in pllarc2 48 in pllavdd 49 v pllavss 47 v pllbgnd 151 v pllbrc1 152 in pllbrc2 154 in pllbvdd 155 v pllbvss 153 v plock y 168 s/t/s ppout0 159 in ppout1 160 in pwrok 62 in ras0 y 127 out ras1 y 125 out ras2 y 126 out ras3 y 124 out ras4 y 128 out ras5 y 123 out ras6 y 105 out (82434nx only) ras7 y 106 out (82434nx only) 184
82434LX/82434nx table 21. 82434LX alphabetical pin assignment (continued) pin name pin y type req y 194 out serr y 172 s/o/d smiact y 69 in stop y 167 s/t/s testen 63 in trdy y 141 s/t/s v dd 20 v v dd (82434LX) 23 v v dd3 (82434nx) v dd (82434LX) 35 v v dd3 (82434nx) v dd (82434LX) 43 v v dd3 (82434nx) v dd 73 v v dd (82434LX) 74 v v dd3 (82434nx) v dd (82434LX) 86 v v dd3 (82434nx) v dd (82434LX) 102 v v dd3 (82434nx) pin name pin y type v dd 103 v v dd 120 v v dd 130 v v dd 139 v v dd 149 v v dd 158 v v dd 176 v v dd 188 v v dd 208 v v ss 1v v ss 24 v v ss 36 v v ss 44 v v ss 51 v v ss 75 v v ss 83 v pin name pin y type v ss 92 v v ss 104 v v ss 107 v v ss 115 v v ss 129 v v ss 140 v v ss 148 v v ss 150 v v ss 157 v v ss 166 v v ss 177 v v ss 189 v v ss 190 v w/r y 67 in we y 108 out 185
82434LX/82434nx table 22. numerical pin assignment pin y pin name type 1v ss v 2 a28 t/s 3 a24 t/s 4 a22 t/s 5 a26 t/s 6 a19 t/s 7 a20 t/s 8 a25 t/s 9 a4 t/s 10 a5 t/s 11 a6 t/s 12 a3 t/s 13 a8 t/s 14 a7 t/s 15 a10 t/s 16 a9 t/s 17 a12 t/s 18 a11 t/s 19 a13 t/s 20 v dd v 21 a14 t/s 22 a15 t/s 23 v dd (82434LX) v v dd3 (82434nx) 24 v ss v 25 cpurst out 26 init out 27 pen y out 28 inv out 29 ken y out 30 boff y out 31 na y out pin y pin name type 32 brdy y out 33 ahold out 34 eads y out 35 v dd (82434LX) v v dd3 (82434nx) 36 v ss v 37 hclkf out 38 hclke out 39 hclkd out 40 hclkc out 41 hclkb out 42 hclka out 43 v dd (82434LX) v v dd3 (82434nx) 44 v ss v 45 pllagnd v 46 pllarc1 in 47 pllavss v 48 pllarc2 in 49 pllavdd v 50 hclkin in 51 v ss v 52 hclkosc in 53 be1 y in 54 be5 y in 55 be4 y in 56 be0 y in 57 be2 y in 58 be6 y in 59 be3 y in 60 be7 y in 61 m/io y in pin y pin name type 62 pwrok in 63 testen in 64 cache y in 65 hitm y in 66 ads y in 67 w/r y in 68 d/c y in 69 smiact y in 70 nc nc 71 hlock y in 72 pchk y in 73 v dd v 74 v dd (82434LX) v v dd3 (82434nx) 75 v ss v 76 caa6 out 77 cab6 out 78 caa5 out 79 cab5 out 80 caa4 out 81 cab4 out 82 caa3 out 83 v ss v 84 cab3 out 85 coe1 y out 86 v dd (82434LX) v v dd3 (82434nx) 87 coe0 y out 88 cadv0 y (82434LX) out cadv0 y /ccs0 y (82434nx) 89 cadv1 y (82434LX) out cadv1 y /ccs1 y (82434nx) 186
82434LX/82434nx table 22. numerical pin assignment (continued) pin y pin name type 90 cwe7 y /cbs7 y out 91 cwe6 y /cbs6 y out 92 v ss v 93 cads0 y ,cr/w0 y out 94 cads1 y ,cr/w1 y out 95 cwe5 y /cbs5 y out 96 cwe4 y /cbs4 y out 97 cwe3 y /cbs3 y out 98 cwe2 y /cbs2 y out 99 cwe1 y /cbs1 y out 100 cwe0 y /cbs0 y out 101 cale out 102 v dd (82434LX) v v dd3 (82434nx) 103 v dd v 104 v ss v 105 nc (82434LX) nc ras6 y (82434nx) out 106 nc (82434LX) nc ras7 y (82434nx) out 107 v ss v 108 we y out 109 nc (82434LX) nc ma11 (82434nx) out 110 ma10 out 111 ma9 out 112 ma8 out 113 ma7 out 114 ma6 out 115 v ss v 116 ma5 out 117 ma4 out 118 ma3 out pin y pin name type 119 ma2 out 120 v dd v 121 ma1 out 122 ma0 out 123 ras5 y out 124 ras3 y out 125 ras1 y out 126 ras2 y out 127 ras0 y out 128 ras4 y out 129 v ss v 130 v dd v 131 cas3 y out 132 cas7 y out 133 cas2 y out 134 cas6 y out 135 cas0 y out 136 cas4 y out 137 cas1 y out 138 cas5 y out 139 v dd v 140 v ss v 141 trdy y s/t/s 142 irdy y s/t/s 143 cbe3 y t/s 144 cbe2 y t/s 145 cbe1 y t/s 146 cbe0 y t/s 147 pcirst y out 148 v ss v 149 v dd v 150 v ss v pin y pin name type 151 pllbgnd v 152 pllbrc1 in 153 pllbvss v 154 pllbrc2 in 155 pllbvdd v 156 pclkin in 157 v ss v 158 v dd v 159 ppout0 in 160 ppout1 in 161 eol in 162 flshreq y in 163 gnt y in 164 memcs y in 165 memreq y in 166 v ss v 167 stop y s/t/s 168 plock y s/t/s 169 perr y s/o/d 170 devsel y s/t/s 171 par t/s 172 serr y s/o/d 173 frame y s/t/s 174 pclkout out 175 mig2 out 176 v dd v 177 v ss v 178 mig1 out 179 mig0 out 180 hig4 out 181 hig3 out 182 hig2 out 187
82434LX/82434nx table 22. numerical pin assignment (continued) pin y pin name type 183 hig1 out 184 hig0 out 185 mdle out 186 drvpci out 187 pig3 out 188 v dd v 189 v ss v 190 v ss v 191 pig2 out pin y pin name type 192 pig1 out 193 pig0 out 194 req y out 195 memack y out 196 a23 t/s 197 a27 t/s 198 a29 t/s 199 a31 t/s 200 a21 t/s pin y pin name type 201 a16 t/s 202 a17 t/s 203 a18 t/s 204 a0 t/s 205 a1 t/s 206 a2 t/s 207 a30 t/s 208 v dd v 188
82434LX/82434nx 10.2 package characteristics 290479 97 figure 87. 208-pin quad flatpack (qfp) dimensions table 23. 82434LX package dimensions symbol description value (mm) a seating height 3.5 (max) a1 stand-off height 0.20 0.50 a2 package height 3.0 (nominal) b lead width 0.18 a 0.1/ b 0.05 d package length and 30.6 g 0.3 width, including pins d1 package length and 28 g 0.1 width, excluding pins e linear lead pitch 0.5 g 0.1 g lead coplanarity 0.1 (max) l lead length 0.5 g 0.2 i lead angle 0 10 table 24. 82434nx package dimensions symbol description value (mm) a seating height 3.7 (max) a1 stand-off height 0.05 0.50 a2 package height 3.45 (max) b lead width 0.13 0.27 d package length and 30.6 g 0.3 width, including pins d1 package length and 28 g 0.1 width, excluding pins e linear lead pitch 0.5 (nominal) g lead coplanarity 0.1 (max) l lead length 0.5 g 0.2 i lead angle 0 10 189
82434LX/82434nx 11.0 testability a nand tree is provided in the 82434LX and 82434nx pcmcs for automated test equipment (ate) board level testing. the nand tree allows the tester to test the connectivity of a subset of the pcmc signal pins. for the 82434LX, the output of the nand tree is driven on pin 109. the nand tree is enabled when a24 e 1, a25 e 0, a26 e 1, and testen e 1atthe rising edge of pwrok. pll bypass mode is en- abled when a24 e 1, and testen e 1 at the rising edge of pwrok. in pll bypass mode, the 82434LX and 82434nx pcmc ac specifications are affected as follows: 1. output valid delays increase by 20 ns. 2. all hold times are 20 ns. 3. setup times and propagation delays are unaffected. 4. input clock high and low times are 100 ns. in both the nand tree test mode and pll bypass mode, testen must remain asserted throughout the testing. a [ 28:24 ] should be set up at least 1 hclk before the rising edge of pwrok and held at least 3 hclks after pwrok. table 11 shows the order of the nand tree inside the pcmc. when not in nand tree test mode, the 82434LX drives the output of the host clock pll onto pin 109. 82434nx test modes the state of a [ 28:24 ] , testen, cpurst, and pwrok can place the 82434nx pcmc into two test modes. when pwrok is low, a [ 27:24 ] and testen directly control the mode of operation of the pcmc. when pwrok is high, the state of a [ 27:24 ] and testen are latched and the pcmc remains in the indicated mode until pwrok is again negated. the high order lbx samples the state of a27 on the falling edge of cpurst. when pwrok is low and both testen and a27 are low, the 82434nx drives ma11 onto pin 109. if both testen and a27 are low when pwrok tran- sitions from low to high, the pcmc continues to drive ma11 onto pin 109. if the high order lbx sam- ples a27 low on the falling edge of cpurst, it will tri-state pin 123. when pwrok is low, testen is low, and a27 is high the pcmc drives the output of the host clock pll onto pin 109. observing pin 109 when in this mode indicates if the host clock pll has locked onto the correct frequency. if testen is low and a27 is high when pwrok transitions from low to high the pcmc continues to drive the output of the host clock pll onto pin 109, regardless of the val- ues of testen and a27. if the high order lbx sam- ples a27 high on the falling edge of cpurst, it drives the output of its host clock pll onto pin 123. no phase delay information can be inferred from these outputs. when pwrok is low, testen is high, a26 is high, a25 is low, a28 is high and a24 is high, the pcmc will drive the output of the nand tree onto pin 109. if testen is high, a26 is high, and a25 is low when pwrok transitions from low to high, the pcmc con- tinues to drive the output of the nand tree onto pin 109. a27 must be pulled low via a pulldown resistor to ground for normal operation. 190
82434LX/82434nx table 25. nand tree order order pin y signal 1 141 trdy y 2 142 irdy y 3 143 cbe3 y 4 144 cbe2 y 5 145 cbe1 y 6 146 cbe0 y 7 159 ppout0 8 160 ppout1 9 161 eol 10 162 flshbuf y 11 163 gnt y 12 164 memcs y 13 165 memreq y 14 167 stop y 15 168 plock y 16 169 perr y 17 170 devsel y 18 171 par 19 172 serr y 20 173 frame y 21 194 req y 22 196 a23 23 197 a27 24 198 a29 order pin y signal 25 199 a31 26 200 a21 27 201 a16 28 202 a17 29 203 a18 30 204 a0 31 205 a1 32 206 a2 33 207 a30 34 2 a28 35 3 a24 36 4 a22 37 5 a26 38 6 a19 39 7 a20 40 8 a25 41 9 a4 42 10 a5 43 11 a6 44 12 a3 45 13 a8 46 14 a7 47 15 a10 48 16 a9 order pin y signal 49 17 a12 50 18 a11 51 19 a13 52 21 a14 53 22 a15 54 53 be1 y 55 54 be5 y 56 55 be4 y 57 56 be0 y 58 57 be2 y 59 58 be6 y 60 59 be3 y 61 60 be7 y 62 61 m/io y 63 64 cache y 64 65 hitm y 65 66 ads y 66 67 w/r y 67 68 d/c y 68 69 smiact y 69 71 hlock y 70 72 pchk y 71 63 testen additional testing notes: 1. hclkout [ 6:1 ] can be toggled via hclkin. 2. cax [ 6:3 ] are flow through outputs via a [ 6:3 ] after pwrok transitions high. 3. ma [ 10:0 ] are flow through outputs via a [ 13:3 ] after pwrok transitions high. 4. cas [ 7:0 ] y outputs can be tested by performing a dram read cycle. 5. pclkout can be tested in pll bypass mode, frequency is hclk/2. 6. pcirst is the nand tree output of tree cell 6. 7. init is the nand tree output of tree cell 53. 191

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